{"id":3585,"date":"2025-09-30T01:35:28","date_gmt":"2025-09-30T01:35:28","guid":{"rendered":"https:\/\/flj-pcb.com\/?p=3585"},"modified":"2025-09-30T05:59:09","modified_gmt":"2025-09-30T05:59:09","slug":"via-size-backdrill-high-speed-pcb-rules","status":"publish","type":"post","link":"https:\/\/flj-pcb.com\/bs\/via-size-backdrill-high-speed-pcb-rules\/","title":{"rendered":"Putem veli\u010dine, predbu\u0161enja i pravila za visokobrzinske PCB-ove"},"content":{"rendered":"
Via je jedan od klju\u010dnih dijelova vi\u0161eslojne tiskane plo\u010dice (PCB). Na mnogim plo\u010dicama tro\u0161kovi bu\u0161enja \u010dine oko 30\u201340% tro\u0161kova izrade plo\u010dice. Jednostavno re\u010deno, svaka rupa na PCB-u mo\u017ee se nazvati viom. Prema svojoj ulozi, via ima dvije glavne namjene: jedna je uspostavljanje elektri\u010dnih veza izme\u0111u slojeva, a druga je pri\u010dvr\u0161\u0107ivanje ili pozicioniranje komponenti.<\/p>\n\n\n\n
Ako pogledamo proizvodni proces, via-rupe se mogu podijeliti u tri tipa: slijepa via-rupa, zakopana via-rupa i prolazna via-rupa (via-rupa kroz rupu). Slijepa via-rupa po\u010dinje od gornje ili donje povr\u0161ine \u0161tampane plo\u010dice (PCB) i ide prema unutra\u0161njem sloju. Ima odre\u0111enu dubinu i koristi se za povezivanje povr\u0161inskih tragova sa tragovima unutra\u0161njeg sloja. Dubina slijepe via-rupe obi\u010dno ne prelazi odre\u0111eni omjer u odnosu na pre\u010dnik rupe. Ugra\u0111ena via je rupa koja povezuje samo unutra\u0161nje slojeve; ne dose\u017ee nijednu povr\u0161inu plo\u010de. I slijepe i ugra\u0111ene via se prave unutar plo\u010de prije laminacije, i tokom svog formiranja mogu se preklapati preko nekoliko unutra\u0161njih slojeva. Tre\u0107i tip je prolazna via. Ova rupa prolazi cijelim putem kroz plo\u010du. Mo\u017ee se koristiti za unutra\u0161nje povezivanje ili kao rupa za monta\u017eu ili pozicioniranje dijelova. Budu\u0107i da su prolazne rupe lak\u0161e za izradu i jeftinije, ve\u0107ina \u0161tampanih plo\u010dica koristi ih umjesto slijepih ili ukopavanih rupa. U ostatku ovog teksta, osim ako nije druga\u010dije navedeno, rije\u010d \u201cvia\u201d odnosi se na prolaznu rupu.<\/p>\n\n\n\n<\/figure>\n\n\n\n
Putem strukture i za\u0161to je veli\u010dina va\u017ena<\/h2>\n\n\n\n
Sa dizajnerske ta\u010dke gledi\u0161ta, via ima dva glavna dijela. Jedan je rupa bu\u0161ena centrirnim svrdlom. Drugi je pad podru\u010dje oko bu\u0161ene rupe. Veli\u010dine ova dva dijela odre\u0111uju veli\u010dinu vie. Kada PCB treba visoku brzinu i visoku gusto\u0107u, dizajneri \u017eele da vie budu \u0161to manje. Male vie ostavljaju vi\u0161e prostora za rutiranje na plo\u010di. Tako\u0111er, manje vie imaju ni\u017eu parazitsku kapacitivnost, pa su pogodnije za visokobrzinske sklopove.<\/p>\n\n\n\n
Me\u0111utim, smanjenje vija pove\u0107ava tro\u0161kove. Tako\u0111er, veli\u010dina vija se ne mo\u017ee neograni\u010deno smanjivati. Ograni\u010denje proizlazi iz procesa bu\u0161enja i pozlatnje. \u0160to je rupa manja, bu\u0161enje traje du\u017ee i bu\u0161ilica se mo\u017ee vi\u0161e odmaknuti od centra. Tako\u0111er, kada je dubina rupe ve\u0107a od \u0161est puta pre\u010dnika bu\u0161ilice, te\u0161ko je osigurati ravnomjernu pozlatnju zida rupe. Na primjer, normalna \u0161esteroslojna \u0161tampana plo\u010dica ima debljinu (dubinu via) od oko 50 mil. U tim uslovima, fabrika plo\u010dica obi\u010dno mo\u017ee bu\u0161iti do minimalnog pre\u010dnika od oko 8 mil.<\/p>\n\n\n\n
Parazitska kapacitivnost vijke<\/h2>\n\n\n\n
Via ima parazitsku kapacitivnost prema masi. Ako znamo da je promjer otvora za razmak od mase na ravnoj plo\u010di D2, promjer pad-a via-e D1, debljina PCB plo\u010de T i dielektri\u010dna konstanta podloge plo\u010de \u03b5, onda je pribli\u017ena parazitska kapacitivnost via-e:<\/p>\n\n\n\n
C = 1.41 \u00d7 \u03b5 \u00d7 T \u00d7 D1 \/ (D2 \u2212 D1)\n<\/code><\/pre>\n\n\n\n
Ova formula daje razuman procjenu kapacitivnosti veze. Parazitska kapacitivnost uglavnom produ\u017euje vrijeme porasta signala i time smanjuje brzinu kola.<\/p>\n\n\n\n
Upotrijebimo konkretan primjer. Pretpostavimo da je debljina plo\u010de 50 mil. Unutra\u0161nji promjer vije je 10 mil, a promjer pade je 20 mil. Razmak izme\u0111u pade i povr\u0161ine bakra uzemljenja je 32 mil. Koriste\u0107i gornju formulu i uzimaju\u0107i \u03b5 = 4,4, dobijamo:<\/p>\n\n\n\n
Ovaj iznos kapacitivnosti mijenja vrijeme porasta. Ako je karakteristi\u010dni impedans 55 oma, promjena vremena porasta 10%\u201390% uzrokovana ovom kapacitivno\u0161\u0107u je pribli\u017eno:<\/p>\n\n\n\n
Iz ovih brojeva vidimo da parasitska kapacitivnost jedne vijice ima samo mali utjecaj na vrijeme porasta. Ali ako signal pri promjeni slojeva pro\u0111e kroz mnogo vijica, taj se utjecaj zbraja. Tada dizajner mora pa\u017eljivo razmisliti o tome.<\/p>\n\n\n\n
Parazitska indukcija vijke<\/h2>\n\n\n\n
Uz parazitsku kapacitivnost, via tako\u0111er ima i parazitsku indukciju. U visokobrzinskom digitalnom dizajnu \u0161teta od parazitske indukcije via-e \u010desto je ve\u0107a od one uzrokovane parazitskom kapacitivno\u0161\u0107u. Serijska indukcija via-e mo\u017ee oslabiti djelovanje bypass kondenzatora i smanjiti filtracijsku u\u010dinkovitost cijelog napajnog sistema.<\/p>\n\n\n\n
Jednostavna aproksimativna formula za induktansu puta je:<\/p>\n\n\n\n
L = 5,08 \u00d7 h \u00d7 [ ln(4h \/ d) + 1 ]\n<\/code><\/pre>\n\n\n\n
gdje:<\/p>\n\n\n\n
\n
L je induktansa.,<\/li>\n\n\n\n
h je du\u017eina puta,<\/li>\n\n\n\n
d je promjer sredi\u0161njeg burgija.<\/li>\n<\/ul>\n\n\n\n
Iz formule vidimo da pre\u010dnik vije ima mali utjecaj na induktivnost, a du\u017eina vije ima najve\u0107i utjecaj. Koriste\u0107i gore navedeni primjer sa h = 0,050 i d = 0,010, dobijamo:<\/p>\n\n\n\n
Kada je u pitanju visokofrekventna struja, impedansu na ovom nivou ne mo\u017ee se zanemariti. Tako\u0111er, imajte na umu da bypass kondenzator postavljen za povezivanje napojnog sloja i uzemljenja obi\u010dno zahtijeva dva via otvora. To zna\u010di da \u0107e induktansa via biti udvostru\u010dena za ovaj bypass put.<\/p>\n\n\n\n
\u0160ta ovo zna\u010di za projektovanje visokih brzina<\/h2>\n\n\n\n
Iz gornje analize parasitskih puteva vidimo da naizgled jednostavan via mo\u017ee izazvati velike negativne efekte na visokobrzinskom \u0161tampanom plo\u010dici. Da bi se smanjili ovi problemi, dizajneri mogu primijeniti sljede\u0107e mjere.<\/p>\n\n\n\n
\n
Odaberite razumnu veli\u010dinu veze.<\/strong> Razmislite o tro\u0161ku i kvaliteti signala. Na primjer, za PCB-ove memorijskih modula s 6 do 10 slojeva dobro je odabrati via dimenzija 10\/20 mil (bu\u0161enje\/pads). Za neke visokog gustog, male plo\u010de mo\u017eete isprobati vias od 8\/18 mil. Prema trenutnoj tehnologiji te\u0161ko je napraviti vias manje od toga. Za napojne ili uzemljene vias koristite ve\u0107e dimenzije kako biste smanjili impedanciju.<\/li>\n\n\n\n
Koristite tanju dasku ako je mogu\u0107e.<\/strong> Kao \u0161to formule pokazuju, tanja plo\u010da poma\u017ee smanjiti i kapacitivnost i indukativnost vijki.<\/li>\n\n\n\n
Izbjegavajte nepotrebne promjene slojeva.<\/strong> Poku\u0161ajte usmjeriti signale bez prebacivanja slojeva. Drugim rije\u010dima, koristite \u0161to je mogu\u0107e manje vias.<\/li>\n\n\n\n
Postavite pinove za napajanje i masu blizu via-a.<\/strong> Postavite pinove za napajanje i masu blizu njihovih via-a. Dr\u017eite vodove izme\u0111u via-a i pina \u0161to kra\u0107ima, jer du\u017ei vodovi pove\u0107avaju indukanciju. Koristite deblje tragove za napajanje i masu kako biste smanjili impedanciju.<\/li>\n\n\n\n
Postavite utore za uzemljenje u blizini utora za promjenu sloja signala.<\/strong> Postavite ground vias blizu vias gdje signali mijenjaju slojeve. Time signalu osiguravate obli\u017enji povratni put. Tako\u0111er mo\u017eete dodati mnogo dodatnih ground vias ako je potrebno. Ali budite fleksibilni. Model vias o kojem smo ranije govorili pretpostavljao je pad na svakom sloju. U nekim slu\u010dajevima mo\u017eete smanjiti ili ukloniti pade na nekim unutra\u0161njim slojevima. Kada je gusto\u0107a vias vrlo visoka, veliki padi na bakrenom pouru mogu formirati prekinutu petlju. Da biste to ispravili, mo\u017eete premjestiti neke vias ili smanjiti veli\u010dinu pade na odre\u0111enim slojevima.<\/li>\n<\/ol>\n\n\n\n
Visokobrzinski PCB-ovi obi\u010dno koriste vi\u0161e slojeva, a viae su klju\u010dni faktor u dizajnu. Via na PCB-u ima tri dijela: samu rupu, pad oko rupe i zonu izolacije napojnog sloja (razmak na napojnim i masnim ravninama oko viae).<\/p>\n\n\n\n
Evo nekoliko prakti\u010dnih savjeta za vi\u0161eslojne plo\u010de visokih performansi:<\/p>\n\n\n\n
\n
Putem preporuka veli\u010dine<\/strong> Za op\u0107e vi\u0161eslojne plo\u010de umjerene gusto\u0107e, via dimenzija 0,25 mm \/ 0,51 mm \/ 0,91 mm (bu\u0161enje \/ pad \/ izolacija napajanja) je dobar izbor. Za plo\u010de visoke gusto\u0107e, 0,20 mm \/ 0,46 mm \/ 0,86 mm mo\u017ee biti prikladno. Nepokrovljene vije mogu se koristiti u nekim dizajnima. Za vije za napajanje ili masu razmotrite ve\u0107e dimenzije radi smanjenja impedanse.<\/li>\n\n\n\n
Zona izolacije napajanja<\/strong> \u0160to je ve\u0107a povr\u0161ina za izolaciju napajanja, to je bolje. Uzmite u obzir gusto\u0107u vijaka na ravnini. \u010cesto se koristi pravilo D1 = D2 + 0,41, \u0161to zna\u010di da promjer pad-a odgovara promjeru razmaka ravnine plus 0,41 mm. To poma\u017ee da razmak ravnine ostane dovoljno \u0161irok.<\/li>\n\n\n\n
Minimizirajte promjene slojeva<\/strong> Smanjite vias izbjegavanjem nepotrebnih promjena slojeva u ruti signala.<\/li>\n\n\n\n
Koristite tanje daske<\/strong> Thinner boards lower both capacitance and inductance of vias.<\/li>\n\n\n\n
Short and wide power\/ground connections<\/strong> Keep the lead from via to power or ground pin short. Make the traces as wide as practical for power or ground to reduce inductive impedance.<\/li>\n\n\n\n
Ground via stitching near layer-change vias<\/strong> Add ground vias close to vias where a signal moves between layers. This gives the signal a short return path.<\/li>\n<\/ol>\n\n\n\n
Also note via length is a main factor for via inductance. For top and bottom layer through vias, the via length equals the full board thickness. As layer counts increase, board thickness may exceed 5 mm. In high-speed design, via length is usually kept below 2.0 mm to reduce via-related problems. For via lengths greater than 2.0 mm, increasing the via diameter can help restore impedance continuity. When the via length is 1.0 mm or less, the best via diameter is about 0.20 mm to 0.30 mm.<\/p>\n\n\n\n
Backdrilling in PCB production<\/h2>\n\n\n\n
1. What is backdrilling?<\/h3>\n\n\n\n
Backdrilling is a special drill step used on deep-hole boards. For example, in making a 12-layer board we might want to connect layer 1 to layer 9. Normally we drill a through-hole once and then plate. That via then runs from layer 1 to layer 12, but we only need a connection between layer 1 and layer 9. The extra section from layer 10 to layer 12 acts like a stub. This stub affects signal paths and can cause signal integrity problems in communication signals. To remove this extra stub, we drill it out from the back side \u2014 a second drilling step. This is called backdrilling. In practice, manufacturers do not drill out every last bit, because later steps remove some copper and the drill bit has a tapered tip. So the factory usually leaves a very small stub. The leftover stub length is called the B value, and a good B value is usually between 50 \u03bcm and 150 \u03bcm.<\/p>\n\n\n\n<\/figure>\n\n\n\n
2. Why backdrill?<\/h3>\n\n\n\n
Backdrilling gives several benefits:<\/p>\n\n\n\n
\n
It reduces noise and interference.<\/li>\n\n\n\n
It improves signal integrity.<\/li>\n\n\n\n
It can make a local area of the board thinner.<\/li>\n\n\n\n
It reduces the need for buried or blind vias, lowering board complexity.<\/li>\n<\/ol>\n\n\n\n
3. What does backdrilling do?<\/h3>\n\n\n\n
Backdrilling removes the via section that does not help connection or signal transfer. This prevents reflections, scattering, delay, and other effects that cause signal \u201cdistortion.\u201d Research shows that besides design, board material, transmission lines, connectors, and chip packaging, through vias have a large impact on signal integrity.<\/p>\n\n\n\n
4. Backdrilling working principle<\/h3>\n\n\n\n
Backdrilling uses a drill bit that is positioned by sensing the PCB surface. When the drill bit tip touches the copper foil on the board surface, a micro-current is generated. This current tells the machine the board surface height. The machine then drills down to the set depth and stops.<\/p>\n\n\n\n
5. Backdrilling process steps<\/h3>\n\n\n\n
A typical backdrilling process may go like this:<\/p>\n\n\n\n
a. Provide the PCB with registration holes. Use these holes to do the first drilling step (the through-hole). b. After first drill, plate the holes. Before plating, use dry film to protect the registration holes as needed. c. Make the outer layer pattern on the plated board. d. Do pattern plating. Before pattern plating, again treat the registration holes with dry film if needed. e. Use the registration holes from the first drill to position the board for backdrilling. Use a drill bit to drill away the plated sections that need backdrilling. f. After backdrilling, wash the backdrilled holes to remove any drill dust and residues.<\/p>\n\n\n\n
6. Technical features of backdrilled boards<\/h3>\n\n\n\n
Typical technical features include:<\/p>\n\n\n\n
\n
Most backdrilled boards are rigid boards.<\/li>\n\n\n\n
Layer counts usually range from 8 to 50 layers.<\/li>\n\n\n\n
Board thickness is often 2.5 mm or more.<\/li>\n\n\n\n
The thickness-to-diameter ratio is relatively large.<\/li>\n\n\n\n
Board sizes are large.<\/li>\n\n\n\n
The initial drill minimum diameter is usually \u2265 0.3 mm.<\/li>\n\n\n\n
Outer layer traces are few; the board often uses a pinch array for press-fit holes.<\/li>\n\n\n\n
Backdrill holes are usually 0.2 mm larger than the holes to be removed.<\/li>\n\n\n\n
Backdrill depth tolerance is about \u00b10.05 mm.<\/li>\n\n\n\n
If backdrilling must reach down to layer M, then the dielectric thickness from layer M to layer M\u22121 must be at least 0.17 mm.<\/li>\n<\/ol>\n\n\n\n<\/figure>\n\n\n\n
7. Typical applications for backdrilled boards<\/h3>\n\n\n\n
Backdrilled boards are mainly used in areas that need very good signal integrity and large structures. Common fields are communication equipment, large servers, medical electronics, military, and aerospace. Because military and aerospace are sensitive fields, backplanes for these areas are often made by research institutes, R&D centers, or PCB manufacturers with strong background in those fields. In China, most demand for backplanes comes from the communications industry, which is growing fast.<\/p>\n\n\n\n
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Sa\u017eetak<\/h2>\n\n\n\n
In short, vias are simple but crucial. They connect layers, and they also add parasitic capacitance and inductance. These parasitics affect both signal rise time and how well bypass capacitors work. Via length mainly drives inductance. Via size, pad size, and clearance affect capacitance. For high-speed designs use the following checklist:<\/p>\n\n\n\n
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Pick via sizes that fit board density and cost. For many boards 10\/20 mil is good; for denser boards try 8\/18 mil. For power\/ground vias, pick larger sizes.<\/li>\n\n\n\n
Use a thin board if possible. This reduces via parasitics.<\/li>\n\n\n\n
Avoid unnecessary layer changes. Keep routing on the same layer when you can.<\/li>\n\n\n\n
Put power and ground pins near vias and keep connections short and wide.<\/li>\n\n\n\n
Add ground vias near signal vias that change layers to give a short return path.<\/li>\n\n\n\n
For long vias or deep boards, consider backdrilling to remove stubs that harm high-speed signals.<\/li>\n\n\n\n
When via density is very high, consider reducing pad sizes on some internal layers to avoid breaking copper pours.<\/li>\n<\/ul>\n\n\n\n
Follow these rules and think about the whole system, not just a single via. In high-speed design the small details add up. A careful via plan will make your board work better, reduce risk, and save time later in debugging.<\/p>\n\n\n\n
![\"Three](\"https:\/\/flj-pcb.com\/wp-content\/uploads\/2025\/09\/Three-types-of-vias.webp\")
<\/figure>\n\n\n\n![\"backdrilling\"](\"https:\/\/flj-pcb.com\/wp-content\/uploads\/2025\/09\/backdrilling.webp\")
<\/figure>\n\n\n\n![\"backdrilled](\"https:\/\/flj-pcb.com\/wp-content\/uploads\/2025\/09\/backdrilled-board.webp\")
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