{"id":2370,"date":"2025-09-03T01:59:36","date_gmt":"2025-09-03T01:59:36","guid":{"rendered":"https:\/\/flj-pcb.com\/?page_id=2370"},"modified":"2025-09-10T08:44:32","modified_gmt":"2025-09-10T08:44:32","slug":"high-speed-pcb","status":"publish","type":"page","link":"https:\/\/flj-pcb.com\/cs\/pcb-manufacturer\/high-speed-pcb\/","title":{"rendered":"Vysokorychlostn\u00ed PCB"},"content":{"rendered":"
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Vysokorychlostn\u00ed n\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f<\/h1>
Vysokorychlostn\u00edm n\u00e1vrhem DPS se rozum\u00ed jak\u00fdkoli n\u00e1vrh, kde integrita sign\u00e1lu za\u010d\u00edn\u00e1 b\u00fdt ovliv\u0148ov\u00e1na fyzik\u00e1ln\u00edmi vlastnostmi DPS, jako je uspo\u0159\u00e1d\u00e1n\u00ed, balen\u00ed, propojen\u00ed a uspo\u0159\u00e1d\u00e1n\u00ed vrstev.
Modern\u00ed elektronika zvy\u0161uje hranov\u00e9 rychlosti a taktovac\u00ed frekvence. Mnoho digit\u00e1ln\u00edch syst\u00e9m\u016f m\u00e1 dnes frekvence sign\u00e1lu vy\u0161\u0161\u00ed ne\u017e 100 MHz. P\u0159i t\u011bchto rychlostech se na stop\u00e1ch na desk\u00e1ch plo\u0161n\u00fdch spoj\u016f objevuj\u00ed efekty p\u0159enosov\u00fdch linek, kter\u00e9 mohou v\u00e1\u017en\u011b ovlivnit chov\u00e1n\u00ed syst\u00e9mu. Proces n\u00e1vrhu DPS pro vysok\u00e9 rychlosti je proces \u0159e\u0161en\u00ed probl\u00e9m\u016f s integritou sign\u00e1lu, kter\u00e9 vysok\u00e9 rychlosti vytv\u00e1\u0159ej\u00ed. Lid\u00e9 \u010dasto pou\u017e\u00edvaj\u00ed term\u00edn \u201cvysokorychlostn\u00ed deska plo\u0161n\u00fdch spoj\u016f\u201d, co p\u0159esn\u011b je vysokorychlostn\u00ed deska plo\u0161n\u00fdch spoj\u016f?
Jeden z n\u00e1zor\u016f \u0159\u00edk\u00e1, \u017ee digit\u00e1ln\u00ed obvod je vysokorychlostn\u00ed, pokud jeho rychlost dosahuje nebo p\u0159esahuje p\u0159ibli\u017en\u011b 45-50 MHz a sign\u00e1ly s touto rychlost\u00ed tvo\u0159\u00ed v\u00edce ne\u017e t\u0159etinu syst\u00e9mu. Ve skute\u010dnosti jsou harmonick\u00e9 frekvence sign\u00e1lu vy\u0161\u0161\u00ed ne\u017e jeho z\u00e1kladn\u00ed frekvence. Rychl\u00e9 zm\u011bny - n\u00e1b\u011b\u017en\u00e9 a sestupn\u00e9 hrany nebo p\u0159echody - zp\u016fsobuj\u00ed neo\u010dek\u00e1van\u00e9 v\u00fdsledky p\u0159enosu. B\u011b\u017en\u00e9 praktick\u00e9 pravidlo zn\u00ed: je-li zpo\u017ed\u011bn\u00ed \u0161\u00ed\u0159en\u00ed veden\u00ed v\u011bt\u0161\u00ed ne\u017e polovina doby n\u00e1b\u011bhu digit\u00e1ln\u00edho sign\u00e1lu, je tento sign\u00e1l pova\u017eov\u00e1n za vysokorychlostn\u00ed sign\u00e1l a z\u00e1le\u017e\u00ed na \u00fa\u010dinc\u00edch p\u0159enosov\u00e9ho veden\u00ed.
Na p\u0159enosu sign\u00e1lu z\u00e1le\u017e\u00ed v okam\u017eiku, kdy sign\u00e1l zm\u011bn\u00ed stav, nap\u0159\u00edklad b\u011bhem doby n\u00e1b\u011bhu nebo poklesu. Sign\u00e1l pot\u0159ebuje k cest\u011b od ovlada\u010de k p\u0159ij\u00edma\u010di pevn\u011b stanovenou dobu. Pokud je doba cesty krat\u0161\u00ed ne\u017e polovina doby n\u00e1b\u011bhu nebo poklesu, pak jak\u00fdkoli odraz od p\u0159ij\u00edma\u010de doraz\u00ed k ovlada\u010di d\u0159\u00edve, ne\u017e sign\u00e1l dokon\u010d\u00ed zm\u011bnu. Pokud je doba cesty del\u0161\u00ed ne\u017e polovina doby n\u00e1b\u011bhu nebo poklesu, odraz se vr\u00e1t\u00ed po zm\u011bn\u011b. Pokud je odraz velk\u00fd, m\u016f\u017ee sou\u010dtov\u00fd pr\u016fb\u011bh zm\u011bnit logick\u00fd stav.
Stru\u010dn\u011b \u0159e\u010deno, chcete-li navrhnout vysoce kvalitn\u00ed vysokorychlostn\u00ed desku plo\u0161n\u00fdch spoj\u016f, mus\u00edte myslet jak na integritu sign\u00e1lu, tak na integritu nap\u00e1jen\u00ed. Mus\u00edme tak\u00e9 zn\u00e1t rozd\u00edl mezi vysokorychlostn\u00edmi sign\u00e1ly a vysokofrekven\u010dn\u00edmi sign\u00e1ly. P\u0159\u00edm\u00e9 vlivy se obvykle projevuj\u00ed jako probl\u00e9my s integritou sign\u00e1lu, ale hlavn\u00ed p\u0159\u00ed\u010dina \u010dasto souvis\u00ed s integritou nap\u00e1jen\u00ed. Integrita nap\u00e1jen\u00ed p\u0159\u00edmo ovliv\u0148uje kone\u010dnou integritu sign\u00e1lu na desce.
Kdy\u017e za\u010dnete navrhovat desku a objev\u00ed se probl\u00e9my jako zpo\u017ed\u011bn\u00ed, p\u0159eslechy, odrazy nebo ne\u017e\u00e1douc\u00ed vyza\u0159ov\u00e1n\u00ed, jste v oblasti vysokorychlostn\u00edho n\u00e1vrhu desek plo\u0161n\u00fdch spoj\u016f.
N\u00e1vrh vysokorychlostn\u00edch desek plo\u0161n\u00fdch spoj\u016f je rozvr\u017een\u00ed desek plo\u0161n\u00fdch spoj\u016f pro vysokorychlostn\u00ed obvody. Jedn\u00e1 se o obvody, u nich\u017e fyzick\u00e9 \u010d\u00e1sti desky ovliv\u0148uj\u00ed integritu sign\u00e1lu. Mezi tyto fyzick\u00e9 faktory pat\u0159\u00ed rozlo\u017een\u00ed, uspo\u0159\u00e1d\u00e1n\u00ed a propojen\u00ed.
P\u0159i n\u00e1vrhu vysokorychlostn\u00edch desek plo\u0161n\u00fdch spoj\u016f mus\u00edte v\u011bnovat v\u00edce \u010dasu ne\u017e obvykle p\u0159esn\u00e9mu rozm\u00edst\u011bn\u00ed stop, jejich \u0161\u00ed\u0159ce, vzd\u00e1lenosti od ostatn\u00edch sign\u00e1l\u016f a typ\u016fm sou\u010d\u00e1stek, ke kter\u00fdm se stopy p\u0159ipojuj\u00ed.<\/div>

1. Sign\u00e1ly a integrita sign\u00e1lu<\/h2>
A\u0165 u\u017e pracujete na b\u011b\u017en\u00e9m nebo vysokorychlostn\u00edm n\u00e1vrhu desky plo\u0161n\u00fdch spoj\u016f, deska vys\u00edl\u00e1 sign\u00e1ly po stop\u00e1ch ke koncov\u00fdm bod\u016fm. Co jsou tedy vysokorychlostn\u00ed sign\u00e1ly? Existuj\u00ed dva hlavn\u00ed typy: analogov\u00e9 a digit\u00e1ln\u00ed.<\/div>

1.1 Digit\u00e1ln\u00ed sign\u00e1ly<\/h3>
Digit\u00e1ln\u00ed sign\u00e1ly jsou jednodu\u0161\u0161\u00ed ne\u017e analogov\u00e9. Jsou to s\u00e9rie n\u00edzk\u00fdch a vysok\u00fdch \u00farovn\u00ed. M\u016f\u017eete si je p\u0159edstavit jako 0 a 1 nebo jako vypnuto a zapnuto.<\/div>

1.2 Analogov\u00e9 sign\u00e1ly<\/h3>
Analogov\u00e9 sign\u00e1ly se li\u0161\u00ed v\u00edce ne\u017e digit\u00e1ln\u00ed sign\u00e1ly. Mohou kol\u00edsat v kladn\u00fdch i z\u00e1porn\u00fdch hodnot\u00e1ch. Sign\u00e1l se m\u011bn\u00ed amplitudou a frekvenc\u00ed.<\/div>

\u00a0<\/p>

P\u0159i n\u00e1vrhu obvodu m\u011bjte na pam\u011bti tyto b\u011b\u017en\u00e9 probl\u00e9my a jejich \u0159e\u0161en\u00ed, abyste zlep\u0161ili v\u00fdkon desky.<\/div>

2. B\u011b\u017en\u00e9 probl\u00e9my a jejich \u0159e\u0161en\u00ed<\/h2>

2.1 Probl\u00e9my<\/h3>
Vysokorychlostn\u00ed n\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f je velmi citliv\u00fd. B\u011bhem projektu se m\u016f\u017eete setkat s n\u011bkolika probl\u00e9my. Zde jsou t\u0159i b\u011b\u017en\u00e9 probl\u00e9my, na kter\u00e9 je t\u0159eba si d\u00e1t pozor.<\/div>

\u00a0<\/p>

  • \u010casov\u00e1n\u00ed<\/strong>: P\u0159i \u0161patn\u00e9m na\u010dasov\u00e1n\u00ed sign\u00e1lu m\u016f\u017ee doj\u00edt k po\u0161kozen\u00ed dat. Kv\u016fli probl\u00e9m\u016fm s \u010dasov\u00e1n\u00edm se ujist\u011bte, \u017ee ka\u017ed\u00fd sm\u011brovan\u00fd sign\u00e1l a ka\u017ed\u00fd hodinov\u00fd sign\u00e1l p\u0159ich\u00e1z\u00ed ve spr\u00e1vn\u00fd \u010das vzhledem ke v\u0161em ostatn\u00edm sign\u00e1l\u016fm.<\/li>
  • Zkreslen\u00ed<\/strong>: Integrita sign\u00e1lu znamen\u00e1, \u017ee sign\u00e1ly p\u0159ich\u00e1zej\u00ed ve spr\u00e1vn\u00e9m tvaru. Pokud sign\u00e1ly nevypadaj\u00ed v koncov\u00fdch bodech spr\u00e1vn\u011b, pravd\u011bpodobn\u011b do\u0161lo po cest\u011b k jejich zkreslen\u00ed.<\/li>
  • Hluk<\/strong>: Ka\u017ed\u00e1 deska plo\u0161n\u00fdch spoj\u016f vyd\u00e1v\u00e1 n\u011bjak\u00fd hluk. P\u0159\u00edli\u0161 velk\u00fd \u0161um v\u0161ak m\u016f\u017ee po\u0161kodit data. \u0160um se \u010dasto objevuje, kdy\u017e jeden sign\u00e1l ne\u010dekan\u011b zazvon\u00ed a ovlivn\u00ed okoln\u00ed sign\u00e1ly.<\/li><\/ul>

    2.2 \u0158e\u0161en\u00ed<\/h3>
    Tyto probl\u00e9my jsou na\u0161t\u011bst\u00ed ji\u017e zn\u00e1m\u00e9. Jedn\u00e1 se o kl\u00ed\u010dov\u00e9 sou\u010d\u00e1sti vysokorychlostn\u00edho n\u00e1vrhu.<\/div>

    \u00a0<\/p>

    • Impedance<\/strong>: \u0158\u00edzen\u00ed impedance je z\u00e1kladn\u00edm \u0159e\u0161en\u00edm mnoha b\u011b\u017en\u00fdch probl\u00e9m\u016f s deskami plo\u0161n\u00fdch spoj\u016f. Pokud je impedance mezi vys\u00edla\u010dem a p\u0159ij\u00edma\u010dem spr\u00e1vn\u00e1, zlep\u0161\u00ed se kvalita, integrita a citlivost sign\u00e1lu.<\/li>
    • Odpov\u00eddaj\u00edc\u00ed<\/strong>: D\u00e9lkov\u00e9 p\u0159izp\u016fsoben\u00ed pom\u00e1h\u00e1 \u010dasov\u00e1n\u00ed. Pokud p\u0159izp\u016fsob\u00edte d\u00e9lky spojen\u00fdch stop, budou p\u0159ich\u00e1zet spole\u010dn\u011b a z\u016fstanou synchronizov\u00e1ny s hodinami.<\/li>
    • Rozestupy<\/strong>: Ponech\u00e1n\u00ed dostate\u010dn\u00e9ho prostoru mezi stopami pom\u00e1h\u00e1 chr\u00e1nit je p\u0159ed \u0161umem a jin\u00fdm ru\u0161en\u00edm. Neumis\u0165ujte stopy p\u0159\u00edli\u0161 bl\u00edzko sebe, abyste omezili ru\u0161en\u00ed.<\/li><\/ul>

      3. Vysokorychlostn\u00ed rozvr\u017een\u00ed PCB<\/h2>
      Kdy\u017e mluv\u00edme o tom, co d\u011bl\u00e1 desku plo\u0161n\u00fdch spoj\u016f vysokorychlostn\u00ed, nezapome\u0148te, \u017ee plat\u00ed mnoho pravidel pro uspo\u0159\u00e1d\u00e1n\u00ed. V\u010dasn\u00e9 pl\u00e1nov\u00e1n\u00ed rozvr\u017een\u00ed pom\u00e1h\u00e1 udr\u017eet projekt v souladu s harmonogramem a sni\u017euje po\u010det chyb.<\/div>

      3.1 Sch\u00e9ma<\/h3>
      Prvn\u00edm krokem je nakreslit obvod jako sch\u00e9ma. P\u0159i kreslen\u00ed p\u0159em\u00fd\u0161lejte o toku sign\u00e1l\u016f. Sna\u017ete se zachytit p\u0159irozen\u00fd tok zleva doprava a zahr\u0148te co nejv\u00edce u\u017eite\u010dn\u00fdch informac\u00ed.<\/div>

      3.2 Po\u017eadavky<\/h3>
      Napi\u0161te jasn\u00e9 pokyny pro rozvr\u017een\u00ed PCB. Uve\u010fte \u00fa\u010del desky, n\u00e1\u010drt obvodu, rozvr\u017een\u00ed desky, rozm\u00edst\u011bn\u00ed sou\u010d\u00e1stek a rozestupy mezi stopami a obvody. Mo\u017en\u00e1 budete muset tak\u00e9 uv\u00e9st, jak\u00e9 typy sign\u00e1l\u016f se nach\u00e1zej\u00ed v jednotliv\u00fdch vrstv\u00e1ch. Pokud nap\u0159\u00edklad pou\u017e\u00edv\u00e1te RF, zva\u017ete n\u00e1vrh RF PCB. VF sign\u00e1ly maj\u00ed zvl\u00e1\u0161tn\u00ed po\u017eadavky. Do po\u017eadavk\u016f uve\u010fte v\u0161e, co deska pot\u0159ebuje ke spolehliv\u00e9mu fungov\u00e1n\u00ed.<\/div>

      3.3 Um\u00edst\u011bn\u00ed<\/h3>
      Um\u00edst\u011bn\u00ed komponent je jednou z nejd\u016fle\u017eit\u011bj\u0161\u00edch \u010d\u00e1st\u00ed rozvr\u017een\u00ed. Zamyslete se nad t\u00edm, kde se obvody na desce nach\u00e1zej\u00ed a co je obklopuje.<\/div>

      3.4 Power Bypass<\/h3>
      Chcete-li sn\u00ed\u017eit \u0161um ve vysokorychlostn\u00edch obvodech, p\u0159emost\u011bte nap\u00e1jec\u00ed v\u00fdvody zesilova\u010de. Pro vysokorychlostn\u00ed optick\u00e9 zesilova\u010de existuj\u00ed dv\u011b b\u011b\u017en\u00e9 techniky bypassu. Jednou z nich je bypass rail-to-ground, kter\u00fd funguje ve v\u011bt\u0161in\u011b p\u0159\u00edpad\u016f. V n\u011bkter\u00fdch p\u0159\u00edpadech jsou u\u017eite\u010dn\u00e9 dal\u0161\u00ed speci\u00e1ln\u00ed techniky.<\/div>

      3.5 Parazitn\u00ed kapacita<\/h3>
      Parazity jsou zbloudil\u00e9 kondenz\u00e1tory a induktory, kter\u00e9 se vpl\u00ed\u017e\u00ed do vysokorychlostn\u00edho uspo\u0159\u00e1d\u00e1n\u00ed a zp\u016fsobuj\u00ed probl\u00e9my. Snadno se tvo\u0159\u00ed a mohou naru\u0161it konstrukci. Vysokorychlostn\u00ed obvody jsou snadno ovlivn\u011bny parazity.<\/div>

      3.6 Pozemn\u00ed rovina<\/h3>
      Zemn\u00ed rovina slou\u017e\u00ed jako referen\u010dn\u00ed nap\u011bt\u00ed, poskytuje st\u00edn\u011bn\u00ed, pom\u00e1h\u00e1 odv\u00e1d\u011bt teplo a sni\u017euje bludnou induk\u010dnost. Ale pozor: zemn\u00ed rovina m\u016f\u017ee tak\u00e9 p\u0159idat parazitn\u00ed kapacitu. Ve v\u011bt\u0161in\u011b p\u0159\u00edpad\u016f chcete m\u00edt plnou, nep\u0159eru\u0161ovanou zemnic\u00ed rovinu a udr\u017eovat ji souvislou.<\/div>

      3.7 Balen\u00ed<\/h3>
      Optick\u00e9 zesilova\u010de a dal\u0161\u00ed sou\u010d\u00e1stky se dod\u00e1vaj\u00ed v mnoha balen\u00edch. V\u00fdb\u011br obalu ovliv\u0148uje vysokofrekven\u010dn\u00ed v\u00fdkon. Obaly ovliv\u0148uj\u00ed parazity a veden\u00ed stop.<\/div>

      3.8 Trasov\u00e1n\u00ed a st\u00edn\u011bn\u00ed<\/h3>
      Sm\u011brov\u00e1n\u00ed a st\u00edn\u011bn\u00ed sni\u017euj\u00ed ru\u0161en\u00ed mezi sign\u00e1ly. N\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f nab\u00edz\u00ed n\u011bkolik metod sm\u011brov\u00e1n\u00ed a st\u00edn\u011bn\u00ed. Dobr\u00fdm st\u00edn\u011bn\u00edm je zemn\u00edc\u00ed rovina. M\u016f\u017eete tak\u00e9 v\u00e9st stopy ortogon\u00e1ln\u011b na sousedn\u00edch vrstv\u00e1ch, abyste sn\u00ed\u017eili kapacitn\u00ed vazbu a udr\u017eeli stopy d\u00e1le od sebe.<\/div>

      4. Jak zjistit, zda je v\u00e1\u0161 projekt vysokorychlostn\u00ed?<\/h2>
      Neexistuje jedin\u00e9 absolutn\u00ed pravidlo pro to, co se pova\u017euje za vysokorychlostn\u00ed n\u00e1vrh desky plo\u0161n\u00fdch spoj\u016f, ale existuje n\u011bkolik praktick\u00fdch zp\u016fsob\u016f, jak rozhodnout, zda je v\u00e1\u0161 projekt vysokorychlostn\u00ed. Probl\u00e9my s integritou sign\u00e1lu jsou jasn\u00fdm znamen\u00edm. Pokud pracujete na telefonu nebo z\u00e1kladn\u00ed desce, jedn\u00e1 se velmi pravd\u011bpodobn\u011b o vysokorychlostn\u00ed n\u00e1vrh. Siln\u00fdm vod\u00edtkem je tak\u00e9 pou\u017eit\u00ed ur\u010dit\u00fdch technologi\u00ed.<\/div>

      \u00a0<\/p>

      1. M\u00e1 deska vysokorychlostn\u00ed rozhran\u00ed?<\/strong>
        Rychl\u00fd zp\u016fsob, jak zjistit, zda je nutn\u00e9 dodr\u017eovat pravidla vysokorychlostn\u00edho n\u00e1vrhu, je zkontrolovat, zda jsou na desce vysokorychlostn\u00ed rozhran\u00ed. P\u0159\u00edkladem jsou DDR, PCIe a video rozhran\u00ed, jako je DVI nebo HDMI. V\u0161echna tato rozhran\u00ed vy\u017eaduj\u00ed p\u0159\u00edsn\u00e1 pravidla vysokorychlostn\u00edho n\u00e1vrhu. U ka\u017ed\u00e9ho rozhran\u00ed tak\u00e9 uve\u010fte v dokumentaci p\u0159esn\u00e9 specifikace kan\u00e1l\u016f.<\/div><\/li>
      2. Pom\u011br d\u00e9lky stopy a vlnov\u00e9 d\u00e9lky sign\u00e1lu<\/strong>
        B\u011b\u017enou kontrolou je pom\u011br mezi d\u00e9lkou va\u0161\u00ed stopy a vlnovou d\u00e9lkou p\u0159en\u00e1\u0161en\u00fdch sign\u00e1l\u016f. Pokud je d\u00e9lka stopy \u0159\u00e1dov\u011b stejn\u00e1 jako vlnov\u00e1 d\u00e9lka sign\u00e1lu, bude deska pravd\u011bpodobn\u011b pot\u0159ebovat vysokorychlostn\u00ed pravidla. N\u011bkter\u00e9 standardy, nap\u0159\u00edklad DDR, vy\u017eaduj\u00ed, aby d\u00e9lka stopy spl\u0148ovala p\u0159\u00edsn\u00e9 tolerance. Jednoduch\u00e9 pravidlo zn\u00ed: pokud jsou d\u00e9lka stopy a vlnov\u00e1 d\u00e9lka ve stejn\u00e9m \u0159\u00e1du, m\u011bli byste uva\u017eovat o vysokorychlostn\u00edm n\u00e1vrhu.<\/div><\/li>
      3. Desky s bezdr\u00e1tov\u00fdm nebo ant\u00e9nn\u00edm rozhran\u00edm<\/strong>
        U ka\u017ed\u00e9 desky, kter\u00e1 se p\u0159ipojuje k ant\u00e9n\u011b, a\u0165 u\u017e je ant\u00e9na na desce, nebo p\u0159ipojen\u00e1 konektorem, je t\u0159eba v\u011bnovat pozornost vysokorychlostn\u00edmu a r\u00e1diov\u00e9mu n\u00e1vrhu. Ant\u00e9ny pro vozidla tak\u00e9 vy\u017eaduj\u00ed p\u0159\u00edsnou kontrolu impedance a vylad\u011bnou d\u00e9lku stop. Pokud m\u00e1te konektory SMA nebo podobn\u00e9 VF konektory, nasm\u011brujte je s \u0159\u00edzenou impedanc\u00ed tak, aby odpov\u00eddala hodnot\u011b konektoru.<\/div><\/li>
      4. Distribuovan\u00e9 syst\u00e9my a mnoho d\u00edl\u010d\u00edch obvod\u016f<\/strong>
        Pokud je v\u00e1\u0161 projekt distribuovan\u00fd syst\u00e9m slo\u017een\u00fd z mnoha d\u00edl\u010d\u00edch obvod\u016f, kter\u00e9 mohou pracovat nez\u00e1visle uvnit\u0159 v\u011bt\u0161\u00edho syst\u00e9mu, budete pravd\u011bpodobn\u011b tak\u00e9 \u010delit probl\u00e9m\u016fm s vysokorychlostn\u00edmi deskami plo\u0161n\u00fdch spoj\u016f. V\u00edce modul\u016f, mnoho vysokorychlostn\u00edch spoj\u016f a sm\u00ed\u0161en\u00e9 \u010dasov\u00e9 dom\u00e9ny zvy\u0161uj\u00ed pravd\u011bpodobnost, \u017ee budete pot\u0159ebovat p\u00e9\u010di o vysokorychlostn\u00ed n\u00e1vrh.<\/div><\/li><\/ol>

        5. Vysokorychlostn\u00ed deskov\u00e9 materi\u00e1ly<\/h2>
        Term\u00edn \u201cvysokorychlostn\u00ed deskov\u00fd materi\u00e1l\u201d je v oboru b\u011b\u017en\u00fd. Obvykle se j\u00edm ozna\u010duj\u00ed materi\u00e1ly s n\u00edzk\u00fdmi ztr\u00e1tami, kter\u00e9 se pou\u017e\u00edvaj\u00ed pro vysokorychlostn\u00ed desky plo\u0161n\u00fdch spoj\u016f. Tyto materi\u00e1ly maj\u00ed ni\u017e\u0161\u00ed ztr\u00e1tov\u00fd tangens, \u010dasto ozna\u010dovan\u00fd jako Df, ve srovn\u00e1n\u00ed s b\u011b\u017en\u00fdm FR-4. Co je to Df a jak ovliv\u0148uje sign\u00e1ly?
        Kdy\u017e se izola\u010dn\u00ed m\u00e9dium, jako je tkanina ze sklen\u011bn\u00fdch vl\u00e1ken a prysky\u0159ice, nach\u00e1z\u00ed v elektrick\u00e9m poli, nabit\u00e9 \u010d\u00e1stice v m\u00e9diu jsou v\u00e1z\u00e1ny uvnit\u0159 molekul. Vn\u011bj\u0161\u00ed pole zp\u016fsobuje drobn\u00e9 posuny. Dip\u00f3ly v m\u00e9diu se pak vyrovn\u00e1vaj\u00ed s polem. Tento jev je dielektrick\u00e1 polarizace. Energie ztracen\u00e1 b\u011bhem procesu polarizace je dielektrick\u00e1 ztr\u00e1ta. Hodnota Df materi\u00e1lu ud\u00e1v\u00e1, jak velk\u00e9 dielektrick\u00e9 ztr\u00e1ty materi\u00e1l m\u00e1.
        Standardn\u00ed deskov\u00e9 materi\u00e1ly tlum\u00ed sinusov\u00e9 vlny v\u00edce ne\u017e rychl\u00e9 materi\u00e1ly. Tento efekt je siln\u011bj\u0161\u00ed u vy\u0161\u0161\u00edch harmonick\u00fdch frekvenc\u00ed. Digit\u00e1ln\u00ed sign\u00e1ly se skl\u00e1daj\u00ed z mnoha sinusov\u00fdch vln o r\u016fzn\u00fdch frekvenc\u00edch. Pokud jsou tyto sinusov\u00e9 vlny zeslabeny, hrany digit\u00e1ln\u00edho sign\u00e1lu se zhor\u0161uj\u00ed a amplituda kles\u00e1. Degradace hran sni\u017euje \u0161\u00ed\u0159ku p\u00e1sma p\u0159enosov\u00e9ho veden\u00ed a sni\u017euje rezervu sign\u00e1lu. Pou\u017eit\u00ed vysokorychlostn\u00edho materi\u00e1lu sni\u017euje ztr\u00e1ty na jednotku d\u00e9lky. P\u0159i stejn\u00e9 d\u00e9lce trasy poskytuje vysokorychlostn\u00ed materi\u00e1l v\u011bt\u0161\u00ed \u0161\u00ed\u0159ku p\u00e1sma a v\u011bt\u0161\u00ed rezervu. Nebo p\u0159i stejn\u00e9m rozpo\u010dtu na ztr\u00e1ty umo\u017e\u0148uje pou\u017eit\u00ed vysokorychlostn\u00edho materi\u00e1lu v\u00e9st del\u0161\u00ed stopy a st\u00e1le spl\u0148ovat v\u00fdkon.
        Pomoci m\u016f\u017ee jednoduch\u00e1 analogie. P\u0159edstavte si dv\u011b auta s r\u016fznou spot\u0159ebou paliva. Auto A spot\u0159ebuje 22 litr\u016f na 100 km (Df: 0,022). Lid\u00e9 mu \u0159\u00edkaj\u00ed \u017erout benz\u00ednu. Auto B spot\u0159ebuje 4,5 litru na 100 km (Df: 0,0045). Lid\u00e9 mu \u0159\u00edkaj\u00ed \u0161et\u0159i\u010d paliva. Pokud m\u00e1te k dispozici pouze 50 litr\u016f paliva a v\u00e1\u0161 c\u00edl je vzd\u00e1len 800 km, benz\u00ednov\u00fd \u017erout do n\u011bj nedojede. \u0160et\u0159i\u010d paliva dojede a je\u0161t\u011b mu palivo zbude. Pokud je c\u00edl cesty vzd\u00e1len jen 200 km, m\u016f\u017ee se st\u00e1t, \u017ee spo\u0159i\u010d dojede s mal\u00fdm zbytkem paliva, tak\u017ee rezerva je mal\u00e1 a cesta je riskantn\u00ed, pokud se n\u011bco pokaz\u00ed. \u0160et\u0159i\u010d paliva zvl\u00e1dne cestu s v\u011bt\u0161\u00ed rezervou. Tento p\u0159\u00edklad ukazuje, pro\u010d n\u011bkdy pot\u0159ebujete rychloobr\u00e1tkov\u00e9 materi\u00e1ly. Kdy\u017e jsou rychlosti sign\u00e1lu vysok\u00e9, d\u00e9lka trasy dlouh\u00e1 nebo rozpo\u010det na ztr\u00e1ty je omezen\u00fd, norm\u00e1ln\u00ed materi\u00e1l nemus\u00ed poskytnout dostate\u010dnou rezervu. V takov\u00fdch p\u0159\u00edpadech doporu\u010dujeme vysokorychlostn\u00ed materi\u00e1l.
        Vysokorychlostn\u00ed materi\u00e1ly se dod\u00e1vaj\u00ed v odstup\u0148ovan\u00fdch \u00farovn\u00edch podle Df. Df je pouze vod\u00edtkem. Pro konstruk\u010dn\u00ed pr\u00e1ce v\u017edy pou\u017e\u00edvejte p\u0159esn\u00e1 \u010d\u00edsla z technick\u00e9ho listu materi\u00e1lu.<\/div>

        5.1 B\u011b\u017en\u00e9 kategorie Df (hodnoty jsou typick\u00e9 referen\u010dn\u00ed hodnoty p\u0159i 10 GHz)<\/h3>
        • Standardn\u00ed ztr\u00e1tov\u00fd materi\u00e1l: Df < 0,022 @ 10 GHz<\/li>
        • St\u0159edn\u00ed ztr\u00e1ta materi\u00e1lu: Df < 0,012 @ 10 GHz<\/li>
        • Materi\u00e1l s n\u00edzk\u00fdmi ztr\u00e1tami: Df < 0,008 @ 10 GHz<\/li>
        • Materi\u00e1l s velmi n\u00edzk\u00fdmi ztr\u00e1tami: Df < 0,005 @ 10 GHz<\/li>
        • Materi\u00e1l s velmi n\u00edzk\u00fdmi ztr\u00e1tami: Df < 0,003 @ 10 GHz<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"

          High-speed PCB Design High-speed PCB design means any design where signal integrity starts to be affected by the PCB\u2019s physical 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          High-speed PCB Design<\\\/h1>
          High-speed PCB design means any design where signal integrity starts to be affected by the PCB\\u2019s physical properties, such as layout, packaging, interconnects, and layer stack-up.
          Modern electronics push edge rates and clock speeds higher. Today many digital systems have signal frequencies above 100 MHz. At those speeds, transmission-line effects appear on PCB traces and can seriously affect system behavior. The PCB design process for high speed is the process of solving the signal integrity problems that high speed creates. People use the term \\u201chigh-speed PCB\\u201d a lot, so what exactly is a high-speed PCB board?
          One view says a digital circuit is high speed when its rate reaches or exceeds about 45\\u201350 MHz and signals at that rate make up more than one third of the system. In fact, a signal\\u2019s harmonic frequencies are higher than its base frequency. Fast changes \\u2014 the rising and falling edges or transitions \\u2014 cause unexpected transmission results. A common practical rule is this: if a line\\u2019s propagation delay is greater than half of the digital signal\\u2019s rise time, that signal is treated as a high-speed signal and transmission-line effects matter.
          Signal transfer matters at the instant the signal changes state, for example during rise or fall time. A signal needs a fixed time to travel from driver to receiver. If the travel time is less than half the rise or fall time, then any reflection from the receiver will reach the driver before the signal finishes changing. If the travel time is longer than half the rise or fall time, the reflection returns after the change. If the reflection is large, the summed waveform can change the logic state.
          In short, to design a high-quality high-speed PCB you must think about both signal integrity and power integrity. We also need to know the difference between high-speed signals and high-frequency signals. The direct effects usually show up as signal integrity problems, but the root cause often links back to power integrity. Power integrity directly affects the final signal integrity of the board.
          When you start designing a board and you see trouble like delay, crosstalk, reflection, or unwanted emission, you are in the high-speed PCB design domain.
          High-speed PCB design is the layout of circuit boards for high-speed circuits. These are circuits where the board\\u2019s physical parts affect signal integrity. Those physical factors include layout, stack-up, and interconnects.
          When you do high-speed PCB design you must spend more time than usual on the exact placement of traces, their widths, how close they are to other signals, and the types of parts the traces connect to.<\\\/div>

          1. Signals and Signal Integrity<\\\/h2>
          Whether you work on ordinary or high-speed PCB design, the board sends signals along traces to endpoints. So what are high-speed signals? There are two main types: analog and digital.<\\\/div>

          1.1 Digital Signals<\\\/h3>
          Digital signals are simpler than analog signals. They are a series of low and high levels. You can think of them as 0 and 1, or off and on.<\\\/div>

          1.2 Analog Signals<\\\/h3>
          Analog signals vary more than digital signals. They may swing positive and negative. The signal changes by amplitude and by frequency.<\\\/div>

          \\u00a0<\\\/p>

          When you design a circuit, keep these common problems and fixes in mind to improve board performance.<\\\/div>

          2. Common Problems and Solutions<\\\/h2>

          2.1 Problems<\\\/h3>
          High-speed PCB design is very sensitive. You may meet several problems during a project. Here are three common problems to watch.<\\\/div>

          \\u00a0<\\\/p>

          • Timing<\\\/strong>: If signal timing is wrong you can get corrupted data. Because of timing issues, make sure every routed signal and every clock signal arrives at the right time relative to all other signals.<\\\/li>
          • Distortion<\\\/strong>: Signal integrity means signals arrive in the right shape. If signals do not look right at the endpoints, they likely suffered distortion along the way.<\\\/li>
          • Noise<\\\/strong>: Every PCB makes some noise. But too much noise can corrupt data. Noise often appears when one signal rings unexpectedly and affects nearby signals.<\\\/li><\\\/ul>

            2.2 Solutions<\\\/h3>
            Fortunately, these issues have known fixes. They are key parts of high-speed design.<\\\/div>

            \\u00a0<\\\/p>

            • Impedance<\\\/strong>: Impedance control is a basic fix for many common PCB problems. When the impedance between transmitter and receiver is correct, signal quality, integrity, and sensitivity improve.<\\\/li>
            • Matching<\\\/strong>: Length matching helps timing. If you match the lengths of coupled traces, they will arrive together and stay in sync with the clock.<\\\/li>
            • Spacing<\\\/strong>: Leaving enough space between traces helps protect them from noise and other interference. Avoid placing traces too close to reduce interference.<\\\/li><\\\/ul>

              3. High-speed PCB Layout<\\\/h2>
              When we talk about what makes a PCB high-speed, remember many layout rules apply. Planning layout early helps keep the project on schedule and reduces errors.<\\\/div>

              3.1 Schematic<\\\/h3>
              The first step is to draw the circuit as a schematic. While you draw, think about signal flow. Try to capture a natural left-to-right flow and include as much useful information as you can.<\\\/div>

              3.2 Requirements<\\\/h3>
              Write clear PCB layout instructions. Include the board\\u2019s purpose, a circuit sketch, the board stack-up, component placement, and spacing between traces and circuits. You may also need to note what types of signals go on each layer. For example, if you use RF, consider RF PCB design. RF signals have special needs. Put everything in the requirements that the board needs to work reliably.<\\\/div>

              3.3 Placement<\\\/h3>
              Component placement is one of the most important parts of layout. Think about where circuits sit on the board and what surrounds them.<\\\/div>

              3.4 Power Bypass<\\\/h3>
              To reduce noise in high-speed circuits, bypass amplifier power pins. For high-speed op-amps there are two common bypass techniques. One is rail-to-ground bypass, which works in most cases. Other special techniques are useful in some cases.<\\\/div>

              3.5 Parasitic Capacitance<\\\/h3>
              Parasitics are stray capacitors and inductors that sneak into high-speed layouts and cause problems. They form easily and can break the design. High-speed circuits are easily affected by parasitics.<\\\/div>

              3.6 Ground Plane<\\\/h3>
              A ground plane serves as a reference voltage, provides shielding, helps heat dissipation, and lowers stray inductance. But be careful: a ground plane can also add parasitic capacitance. In most cases you want a full, uninterrupted ground plane and keep it continuous.<\\\/div>

              3.7 Packaging<\\\/h3>
              Op-amps and other parts come in many packages. The package choice affects high-frequency performance. Packages influence parasitics and trace routing.<\\\/div>

              3.8 Routing and Shielding<\\\/h3>
              Routing and shielding reduce interference between signals. PCB design offers several routing and shielding methods. A ground plane is good shielding. You can also route traces orthogonally on adjacent layers to reduce capacitive coupling and keep traces farther apart.<\\\/div>

              4. How to Tell If Your Project Is High-Speed<\\\/h2>
              There is no single, absolute rule for what counts as a high-speed PCB design, but there are several practical ways to decide if your project is high-speed. Signal integrity problems are a clear sign. If you are working on a phone or a motherboard, that very likely is a high-speed design. The use of certain technologies is also a strong clue.<\\\/div>

              \\u00a0<\\\/p>

              1. Does the board have high-speed interfaces?<\\\/strong>
                A quick way to see if you must follow high-speed design rules is to check for high-speed interfaces on the board. Examples are DDR, PCIe, and video interfaces such as DVI or HDMI. All of these interfaces need strict high-speed design rules. Also, for each interface, include exact channel specs in your documentation.<\\\/div><\\\/li>
              2. Ratio of trace length to signal wavelength<\\\/strong>
                A common check is the ratio between your trace length and the wavelength of the signals you carry. If the trace length is on the same order as the signal wavelength, the board will likely need high-speed rules. Some standards, like DDR, require trace lengths to meet tight tolerances. A simple rule of thumb is: if trace length and wavelength are within the same order of magnitude, you should consider high-speed design.<\\\/div><\\\/li>
              3. Boards with wireless or antenna interfaces<\\\/strong>
                Every board that connects to an antenna, whether the antenna is on the board or attached by a connector, needs careful attention to high-speed and RF design. Vehicle antennas also need tight impedance control and tuned trace lengths. If you have SMA connectors or similar RF connectors, route them with controlled impedance to match the connector value.<\\\/div><\\\/li>
              4. Distributed systems and many subcircuits<\\\/strong>
                If your project is a distributed system made of many subcircuits that can operate independently inside a larger system, you will also likely face high-speed PCB challenges. Multiple modules, many high-speed links, and mixed timing domains raise the chance you need high-speed design care.<\\\/div><\\\/li><\\\/ol>

                5. High-speed Board Materials<\\\/h2>
                The term \\u201chigh-speed board material\\u201d is common in the industry. It usually means low-loss materials that are used for high-speed PCBs. These materials have a lower loss tangent, often called Df, compared with ordinary FR-4. What is Df and how does it affect signals?
                When an insulating medium like glass fiber cloth and resin sits in an electric field, the charged particles in the medium are bound inside molecules. The external field makes tiny displacements. Dipoles in the medium then align with the field. This effect is dielectric polarization. The energy lost during the polarization process is dielectric loss. The material Df value measures how much dielectric loss the material has.
                Standard board materials attenuate sine waves more than high-speed materials do. The effect is stronger at higher harmonic frequencies. Digital signals are made of many sine waves at different frequencies. If those sine waves are attenuated, the edges of the digital signal degrade and the amplitude falls. Edge degradation reduces the transmission line bandwidth and lowers signal margin. Using a high-speed material reduces loss per unit length. For the same trace length, a high-speed material gives higher bandwidth and more margin. Or, for the same loss budget, using high-speed material lets you route longer traces and still meet performance.
                A simple analogy may help. Imagine two cars with different fuel consumption. Car A uses 22 liters per 100 km (Df: 0.022). People call it a gas guzzler. Car B uses 4.5 liters per 100 km (Df: 0.0045). People call it a fuel saver. If you have only 50 liters of fuel and your destination is 800 km away, the gas guzzler will not reach it. The fuel saver will reach and still have fuel left. If the destination is only 200 km, the gas guzzler may reach with little fuel left, so the margin is small and the trip is risky if something goes wrong. The fuel saver handles the trip with better margin. This example shows why you sometimes need high-speed materials. When signal rates are high, trace lengths are long, or the loss budget is tight, normal material may not give enough margin. In such cases, we recommend high-speed material.
                High-speed materials come in graded levels based on Df. Df is only a guide. Always use the exact numbers from the material data sheet for design work.<\\\/div>

                5.1 Common Df Categories (values are typical references at 10 GHz)<\\\/h3>
                • Standard loss material: Df < 0.022 @ 10 GHz<\\\/li>
                • Mid loss material: Df < 0.012 @ 10 GHz<\\\/li>
                • Low loss material: Df < 0.008 @ 10 GHz<\\\/li>
                • Very low loss material: Df < 0.005 @ 10 GHz<\\\/li>
                • Ultra low loss material: Df < 0.003 @ 10 GHz<\\\/li><\\\/ul>\",\"display_condition_list\":[{\"display_condition_login_status\":\"subscriber\",\"_id\":\"20fe95e\"}]},\"elements\":[],\"widgetType\":\"text-editor\"}],\"isInner\":false}]"],"_elementor_conditions":["a:0:{}"],"_edit_last":["1"],"_elementor_version":["3.31.2"],"_elementor_pro_version":["3.31.2"],"_astra_content_layout_flag":["disabled"],"ast-title-bar-display":["disabled"],"_wp_page_template":["default"],"_elementor_page_settings":["a:0:{}"],"rank_math_internal_links_processed":["1"],"rank_math_news_sitemap_robots":["index"],"rank_math_robots":["a:1:{i:0;s:5:\"index\";}"],"_uag_page_assets":["a:9:{s:3:\"css\";s:30187:\".uag-blocks-common-selector{z-index:var(--z-index-desktop) !important}@media (max-width: 976px){.uag-blocks-common-selector{z-index:var(--z-index-tablet) !important}}@media (max-width: 767px){.uag-blocks-common-selector{z-index:var(--z-index-mobile) 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IGNvbXBvbmVudCBwbGFjZW1lbnQsIGFuZCBzcGFjaW5nIGJldHdlZW4gdHJhY2VzIGFuZCBjaXJjdWl0cy4gWW91IG1heSBhbHNvIG5lZWQgdG8gbm90ZSB3aGF0IHR5cGVzIG9mIHNpZ25hbHMgZ28gb24gZWFjaCBsYXllci4gRm9yIGV4YW1wbGUsIGlmIHlvdSB1c2UgUkYsIGNvbnNpZGVyIFJGIFBDQiBkZXNpZ24uIFJGIHNpZ25hbHMgaGF2ZSBzcGVjaWFsIG5lZWRzLiBQdXQgZXZlcnl0aGluZyBpbiB0aGUgcmVxdWlyZW1lbnRzIHRoYXQgdGhlIGJvYXJkIG5lZWRzIHRvIHdvcmsgcmVsaWFibHkuPFwvZGl2PjxoMyBjbGFzcz1cImhlYWRlci12ZkM2QVYgYXV0by1oaWRlLWxhc3Qtc2libGluZy1iclwiPjMuMyBQbGFjZW1lbnQ8XC9oMz48ZGl2IGNsYXNzPVwiYXV0by1oaWRlLWxhc3Qtc2libGluZy1iciBwYXJhZ3JhcGgtSk9US1hBIHBhcmFncmFwaC1lbGVtZW50IGJyLXBhcmFncmFwaC1zcGFjZVwiPkNvbXBvbmVudCBwbGFjZW1lbnQgaXMgb25lIG9mIHRoZSBtb3N0IGltcG9ydGFudCBwYXJ0cyBvZiBsYXlvdXQuIFRoaW5rIGFib3V0IHdoZXJlIGNpcmN1aXRzIHNpdCBvbiB0aGUgYm9hcmQgYW5kIHdoYXQgc3Vycm91bmRzIHRoZW0uPFwvZGl2PjxoMyBjbGFzcz1cImhlYWRlci12ZkM2QVYgYXV0by1oaWRlLWxhc3Qtc2libGluZy1iclwiPjMuNCBQb3dlciBCeXBhc3M8XC9oMz48ZGl2IGNsYXNzPVwiYXV0by1oaWRlLWxhc3Qtc2libGluZy1iciBwYXJhZ3JhcGgtSk9US1hBIHBhcmFncmFwaC1lbGVtZW50IGJyLXBhcmFncmFwaC1zcGFjZVwiPlRvIHJlZHVjZSBub2lzZSBpbiBoaWdoLXNwZWVkIGNpcmN1aXRzLCBieXBhc3MgYW1wbGlmaWVyIHBvd2VyIHBpbnMuIEZvciBoaWdoLXNwZWVkIG9wLWFtcHMgdGhlcmUgYXJlIHR3byBjb21tb24gYnlwYXNzIHRlY2huaXF1ZXMuIE9uZSBpcyByYWlsLXRvLWdyb3VuZCBieXBhc3MsIHdoaWNoIHdvcmtzIGluIG1vc3QgY2FzZXMuIE90aGVyIHNwZWNpYWwgdGVjaG5pcXVlcyBhcmUgdXNlZnVsIGluIHNvbWUgY2FzZXMuPFwvZGl2PjxoMyBjbGFzcz1cImhlYWRlci12ZkM2QVYgYXV0by1oaWRlLWxhc3Qtc2libGluZy1iclwiPjMuNSBQYXJhc2l0aWMgQ2FwYWNpdGFuY2U8XC9oMz48ZGl2IGNsYXNzPVwiYXV0by1oaWRlLWxhc3Qtc2libGluZy1iciBwYXJhZ3JhcGgtSk9US1hBIHBhcmFncmFwaC1lbGVtZW50IGJyLXBhcmFncmFwaC1zcGFjZVwiPlBhcmFzaXRpY3MgYXJlIHN0cmF5IGNhcGFjaXRvcnMgYW5kIGluZHVjdG9ycyB0aGF0IHNuZWFrIGludG8gaGlnaC1zcGVlZCBsYXlvdXRzIGFuZCBjYXVzZSBwcm9ibGVtcy4gVGhleSBmb3JtIGVhc2lseSBhbmQgY2FuIGJyZWFrIHRoZSBkZXNpZ24uIEhpZ2gtc3BlZWQgY2lyY3VpdHMgYXJlIGVhc2lseSBhZmZlY3RlZCBieSBwYXJhc2l0aWNzLjxcL2Rpdj48aDMgY2xhc3M9XCJoZWFkZXItdmZDNkFWIGF1dG8taGlkZS1sYXN0LXNpYmxpbmctYnJcIj4zLjYgR3JvdW5kIFBsYW5lPFwvaDM+PGRpdiBjbGFzcz1cImF1dG8taGlkZS1sYXN0LXNpYmxpbmctYnIgcGFyYWdyYXBoLUpPVEtYQSBwYXJhZ3JhcGgtZWxlbWVudCBici1wYXJhZ3JhcGgtc3BhY2VcIj5BIGdyb3VuZCBwbGFuZSBzZXJ2ZXMgYXMgYSByZWZlcmVuY2Ugdm9sdGFnZSwgcHJvdmlkZXMgc2hpZWxkaW5nLCBoZWxwcyBoZWF0IGRpc3NpcGF0aW9uLCBhbmQgbG93ZXJzIHN0cmF5IGluZHVjdGFuY2UuIEJ1dCBiZSBjYXJlZnVsOiBhIGdyb3VuZCBwbGFuZSBjYW4gYWxzbyBhZGQgcGFyYXNpdGljIGNhcGFjaXRhbmNlLiBJbiBtb3N0IGNhc2VzIHlvdSB3YW50IGEgZnVsbCwgdW5pbnRlcnJ1cHRlZCBncm91bmQgcGxhbmUgYW5kIGtlZXAgaXQgY29udGludW91cy48XC9kaXY+PGgzIGNsYXNzPVwiaGVhZGVyLXZmQzZBViBhdXRvLWhpZGUtbGFzdC1zaWJsaW5nLWJyXCI+My43IFBhY2thZ2luZzxcL2gzPjxkaXYgY2xhc3M9XCJhdXRvLWhpZGUtbGFzdC1zaWJsaW5nLWJyIHBhcmFncmFwaC1KT1RLWEEgcGFyYWdyYXBoLWVsZW1lbnQgYnItcGFyYWdyYXBoLXNwYWNlXCI+T3AtYW1wcyBhbmQgb3RoZXIgcGFydHMgY29tZSBpbiBtYW55IHBhY2thZ2VzLiBUaGUgcGFja2FnZSBjaG9pY2UgYWZmZWN0cyBoaWdoLWZyZXF1ZW5jeSBwZXJmb3JtYW5jZS4gUGFja2FnZXMgaW5mbHVlbmNlIHBhcmFzaXRpY3MgYW5kIHRyYWNlIHJvdXRpbmcuPFwvZGl2PjxoMyBjbGFzcz1cImhlYWRlci12ZkM2QVYgYXV0by1oaWRlLWxhc3Qtc2libGluZy1iclwiPjMuOCBSb3V0aW5nIGFuZCBTaGllbGRpbmc8XC9oMz48ZGl2IGNsYXNzPVwiYXV0by1oaWRlLWxhc3Qtc2libGluZy1iciBwYXJhZ3JhcGgtSk9US1hBIHBhcmFncmFwaC1lbGVtZW50IGJyLXBhcmFncmFwaC1zcGFjZVwiPlJvdXRpbmcgYW5kIHNoaWVsZGluZyByZWR1Y2UgaW50ZXJmZXJlbmNlIGJldHdlZW4gc2lnbmFscy4gUENCIGRlc2lnbiBvZmZlcnMgc2V2ZXJhbCByb3V0aW5nIGFuZCBzaGllbGRpbmcgbWV0aG9kcy4gQSBncm91bmQgcGxhbmUgaXMgZ29vZCBzaGllbGRpbmcuIFlvdSBjYW4gYWxzbyByb3V0ZSB0cmFjZXMgb3J0aG9nb25hbGx5IG9uIGFkamFjZW50IGxheWVycyB0byByZWR1Y2UgY2FwYWNpdGl2ZSBjb3VwbGluZyBhbmQga2VlcCB0cmFjZXMgZmFydGhlciBhcGFydC48XC9kaXY+PGgyIGNsYXNzPVwiaGVhZGVyLXZmQzZBViBhdXRvLWhpZGUtbGFzdC1zaWJsaW5nLWJyXCI+NC4gSG93IHRvIFRlbGwgSWYgWW91ciBQcm9qZWN0IElzIEhpZ2gtU3BlZWQ8XC9oMj48ZGl2IGNsYXNzPVwiYXV0by1oaWRlLWxhc3Qtc2libGluZy1iciBwYXJhZ3JhcGgtSk9US1hBIHBhcmFncmFwaC1lbGVtZW50IGJyLXBhcmFncmFwaC1zcGFjZVwiPlRoZXJlIGlzIG5vIHNpbmdsZSwgYWJzb2x1dGUgcnVsZSBmb3Igd2hhdCBjb3VudHMgYXMgYSBoaWdoLXNwZWVkIFBDQiBkZXNpZ24sIGJ1dCB0aGVyZSBhcmUgc2V2ZXJhbCBwcmFjdGljYWwgd2F5cyB0byBkZWNpZGUgaWYgeW91ciBwcm9qZWN0IGlzIGhpZ2gtc3BlZWQuIFNpZ25hbCBpbnRlZ3JpdHkgcHJvYmxlbXMgYXJlIGEgY2xlYXIgc2lnbi4gSWYgeW91IGFyZSB3b3JraW5nIG9uIGEgcGhvbmUgb3IgYSBtb3RoZXJib2FyZCwgdGhhdCB2ZXJ5IGxpa2VseSBpcyBhIGhpZ2gtc3BlZWQgZGVzaWduLiBUaGUgdXNlIG9mIGNlcnRhaW4gdGVjaG5vbG9naWVzIGlzIGFsc28gYSBzdHJvbmcgY2x1ZS48XC9kaXY+PHA+XHUwMGEwPFwvcD48b2wgY2xhc3M9XCJhdXRvLWhpZGUtbGFzdC1zaWJsaW5nLWJyXCI+PGxpPjxkaXYgY2xhc3M9XCJhdXRvLWhpZGUtbGFzdC1zaWJsaW5nLWJyIHBhcmFncmFwaC1KT1RLWEEgcGFyYWdyYXBoLWVsZW1lbnQgYnItcGFyYWdyYXBoLXNwYWNlXCI+PHN0cm9uZz5Eb2VzIHRoZSBib2FyZCBoYXZlIGhpZ2gtc3BlZWQgaW50ZXJmYWNlcz88XC9zdHJvbmc+PGJyIGNsYXNzPVwiY29udGFpbmVyLXV0bG5XMiB3cmFwcGVyLWQwQ2MxayB1bmRlZmluZWRcIiBcLz5BIHF1aWNrIHdheSB0byBzZWUgaWYgeW91IG11c3QgZm9sbG93IGhpZ2gtc3BlZWQgZGVzaWduIHJ1bGVzIGlzIHRvIGNoZWNrIGZvciBoaWdoLXNwZWVkIGludGVyZmFjZXMgb24gdGhlIGJvYXJkLiBFeGFtcGxlcyBhcmUgRERSLCBQQ0llLCBhbmQgdmlkZW8gaW50ZXJmYWNlcyBzdWNoIGFzIERWSSBvciBIRE1JLiBBbGwgb2YgdGhlc2UgaW50ZXJmYWNlcyBuZWVkIHN0cmljdCBoaWdoLXNwZWVkIGRlc2lnbiBydWxlcy4gQWxzbywgZm9yIGVhY2ggaW50ZXJmYWNlLCBpbmNsdWRlIGV4YWN0IGNoYW5uZWwgc3BlY3MgaW4geW91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