{"id":4751,"date":"2026-03-03T09:46:50","date_gmt":"2026-03-03T09:46:50","guid":{"rendered":"https:\/\/flj-pcb.com\/?p=4751"},"modified":"2026-03-03T10:04:27","modified_gmt":"2026-03-03T10:04:27","slug":"pcb-stackup-function-and-design-principles-translation","status":"publish","type":"post","link":"https:\/\/flj-pcb.com\/en\/pcb-stackup-function-and-design-principles-translation\/","title":{"rendered":"Multilayer PCB Stackup Best Practices for Signal Integrity"},"content":{"rendered":"

1. Definition and When to Add Layers<\/h2>\n\n\n\n

For high-speed multilayer boards<\/a>, a basic two-layer design often cannot meet the needs for signal quality and routing density. In that case, you need to add layers to the PCB stackup to meet the design needs.<\/p>\n\n\n\n

2. Positive (signal) planes and negative (inverted) planes<\/h2>\n\n\n\n

A positive plane is the usual signal layer used for routing. The visible parts are copper traces. On a positive plane you can do large copper pours and fill areas with copper, for example using terms like \u201ctrace\u201d or \u201ccopper\u201d to describe the copper areas. See Figure 8-32.<\/p>\n\n\n\n

\"8-32
8-32 Positive Plane Layer<\/figcaption><\/figure><\/div>\n\n\n\n

A negative plane is the opposite. With a negative plane, the default is to pour copper across the whole layer. The routing areas are the cutouts. There is no copper on the routing lines. What you do is carve out the copper and then set the nets for the carved areas. See Figure 8-33.<\/p>\n\n\n\n

\"Figure
Figure 8-33 Negative Plane Layer<\/figcaption><\/figure><\/div>\n\n\n\n

3. Splitting inner power\/ground planes<\/h2>\n\n\n\n

In older Protel versions, inner power planes were split using a \u201csplit\u201d function. In current versions such as Altium Designer 19<\/a>, you split by drawing \u201clines\u201d and use the hotkey \u201cPL\u201d to place them. The split lines should not be too thin. You can choose 15 mil or larger. When you pour copper after splitting, draw a closed polygon with the \u201cline\u201d tool, then double-click inside the polygon and set the net for the copper pour. See Figure 8-34.<\/p>\n\n\n\n

\"Figure
Figure 8-34 Double-Click to Assign Net<\/figcaption><\/figure><\/div>\n\n\n\n

Both positive and negative planes can be used for inner power or ground layers. You can also achieve a positive inner plane by routing and copper pours. The advantage of a negative plane is that you start with a large poured copper area by default. Then you add vias or change pour sizes without re-pouring the whole layer. This saves time in copper pour recalculation. When inner layers are used as power and ground planes (also called ground plane or return plane), the layers are mostly large copper pours. The advantage of using negative planes is clear here.<\/p>\n\n\n\n

4. Understanding PCB Stackup<\/h2>\n\n\n\n

As high-speed circuits become more common, PCB complexity grows. To avoid electrical interference, signal layers and power layers must be separated. That leads to multilayer PCB design. Before designing a multilayer PCB, the designer must first decide the board structure based on circuit size, board dimensions, and electromagnetic compatibility (EMC) requirements. In other words, decide whether to use a 4-layer, 6-layer, or more layer board. This is a basic idea of multilayer board design.<\/p>\n\n\n\n

After deciding the number of layers, the next step is to place inner power and ground layers and to decide how to distribute different signal types across those layers. That choice is the stackup selection. Stackup structure is an important factor that affects PCB EMC performance. A good stackup design can greatly reduce electromagnetic interference (EMI) and crosstalk<\/a>.<\/p>\n\n\n\n

More layers are not always better, and fewer layers are not always better. Choosing a multilayer stackup requires weighing many factors. From the routing point of view, more layers make routing easier. But manufacturing cost and difficulty also rise. For manufacturers<\/a>, whether the stackup is symmetric is an important concern during fabrication. So layer count must balance all needs.<\/p>\n\n\n\n

Experienced designers usually do a pre-placement of components. Then they analyze routing bottlenecks. They count special routing needs, such as differential pairs and sensitive nets. From that, they decide how many signal layers are needed. Then they decide the number of inner power\/ground layers based on power types, isolation needs, and interference suppression. After this, the total number of board layers is basically fixed.<\/p>\n\n\n\n

5. Common PCB Stackups<\/h2>\n\n\n\n

Once the number of layers is fixed, the next job is to arrange the order of those layers. Figures 8-35 and 8-36 show common stackups for 4-layer and 6-layer boards.<\/p>\n\n\n\n

\n
\n
\"Figure
Figure 8-35 Common 4-Layer Board Stackup Structure<\/figcaption><\/figure><\/div>\n<\/div>\n\n\n\n
\n
\"Figure
Figure 8-36 Common 6-Layer Board Stackup Structure<\/figcaption><\/figure>\n<\/div>\n<\/div><\/div>\n\n\n\n

6. Stackup Analysis<\/h2>\n\n\n\n

How to stack? Which stackup is better? Follow these basic rules:<\/p>\n\n\n\n

Make the component side and the solder side into full ground planes when possible (this gives shielding).<\/p>\n\n\n\n

Avoid adjacent parallel routing layers as much as possible.<\/p>\n\n\n\n

Put all signal layers next to a ground plane when possible.<\/p>\n\n\n\n

Put critical signals next to a ground layer and avoid crossing across split areas.<\/p>\n\n\n\n

Apply these rules to the common stackup examples shown in Figures 8-35 and 8-36. The analysis is as follows.<\/p>\n\n\n\n

(1) Table 8-1 compares the pros and cons of three common 4-layer board stackup schemes.<\/p>\n\n\n\n

Scheme<\/th>Scheme Diagram (ASCII Art)<\/th>Advantages<\/th>Disadvantages<\/th><\/tr><\/thead>
Scheme 1<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 PWR01 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN02 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Ground) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>This scheme is mainly designed to achieve a single-layer shielding effect, with the power plane and ground plane placed on the top and bottom layers respectively.<\/td>(1) The power and ground planes are too far apart, leading to excessive impedance in the power plane;(2) The power and ground planes are highly incomplete due to the influence of component pads and other factors;(3) The incomplete reference plane causes discontinuous signal traces, making it difficult to achieve the expected shielding effect.<\/td><\/tr>
Scheme 2<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR03 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Signal) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>A ground plane is placed under the component side, making it suitable for scenarios where main components are placed on the top layer or key signals are routed on the top layer.<\/td>\/<\/td><\/tr>
Scheme 3<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR02 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND03 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Signal) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Similar to Scheme 2, it is suitable for scenarios where main components are placed on the bottom layer or key signals are routed on the bottom layer.<\/td>\/<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

(2) Table 8-2 compares the pros and cons of four common 6-layer board stackup schemes.<\/p>\n\n\n\n

Scheme<\/th>Scheme Diagram (ASCII Art)<\/th>Advantages<\/th>Disadvantages<\/th><\/tr><\/thead>
Scheme 1<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signal) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Adopts 4 signal layers and two internal power\/ground layers, providing more signal layers to facilitate routing between components.<\/td>(1) The power plane and ground plane are too far apart, resulting in insufficient coupling;(2) Signal layers SIN03 and SIN04 are mainly routed on surface layers, leading to poor signal isolation and crosstalk, requiring staggered routing.<\/td><\/tr>
Scheme 2<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN02 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND03 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR04 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN05 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signal) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>The power plane and ground plane are fully coupled.<\/td>Adjacent layers of surface signal layers are also signal layers, resulting in poor signal isolation and crosstalk.<\/td><\/tr>
Scheme 3<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signal) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>(1) The power plane and ground plane are fully coupled;(2) Each signal layer is directly adjacent to the internal power\/ground plane, providing effective isolation from other signal layers and reducing crosstalk;(3) Signal layer SIN03 is adjacent to two internal planes (GND02 and PWR05), which can effectively shield external interference on SIN03 and crosstalk from SIN03 to other layers.<\/td>\/<\/td><\/tr>
Scheme 4<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signal) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR03 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Ground) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Power) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signal) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>(1) The power plane and ground plane are fully coupled;(2) Each signal layer is directly adjacent to the internal power\/ground plane, providing effective isolation from other signal layers and reducing crosstalk.<\/td>\/<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

From comparing schemes 1 to 4, when signal performance is the top priority, schemes 3 and 4 are clearly better than the first two schemes. But in real product design, cost is a major concern. With high routing density, designers often choose scheme 1 for stackup to save cost. When routing on scheme 1, pay special attention to crossings between two adjacent signal layers and try to reduce crosstalk as much as possible.<\/p>\n\n\n\n

(3) For common 8-layer boards, recommended stackup options are shown in Figure 8-37. Prefer option 1 or option 2. Option 3 is usable.<\/p>\n\n\n\n

\"Figure
Figure 8-37 Recommended Stackup Schemes for Common 8-Layer Boards<\/figcaption><\/figure><\/div>\n\n\n\n

7. Adding and Editing Layers<\/h2>\n\n\n\n

After you confirm the stackup plan, how do you add layers in Altium Designer? A simple example follows.<\/p>\n\n\n\n

Run the menu command \u201cDesign \u2192 Layer Stack Manager\u201d or press the hotkey \u201cDK\u201d to open the Layer Stack Manager. Set the related parameters as shown in Figure 8-38.<\/p>\n\n\n\n

Right-click and choose \u201cInsert layer above\u201d or \u201cInsert layer below\u201d to add a layer. You can add a positive plane or a negative plane. Use \u201cMove layer up\u201d or \u201cMove layer down\u201d to adjust the order of the added layers.<\/p>\n\n\n\n

Double-click the layer name to rename it. You can name layers TOP, GND02, SIN03, SIN04, PWR05, BOTTOM, etc. Altium Designer 19 supports this \u201cletter + layer number\u201d naming. This makes reading and recognition easier.<\/p>\n\n\n\n

Set board and layer thickness according to the stackup.<\/p>\n\n\n\n

To meet the design\u2019s 20H requirement, you can set the negative plane\u2019s keepout amount (inner offset). [Note: the original text uses \u201c20H.\u201d The translator keeps this term as written.]<\/p>\n\n\n\n

Click \u201cOK\u201d to finish stackup settings. An example 4-layer board stackup effect is shown in Figure 8-39.<\/p>\n\n\n\n

\"Figure
Figure 8-39 4-Layer Board Stackup Result<\/figcaption><\/figure><\/div>\n\n\n\n

8. Recommendation<\/h2>\n\n\n\n

It is suggested to treat signal layers as positive planes and to treat power and ground layers as negative planes. This approach can greatly reduce file data size and speed up design work.<\/p>","protected":false},"excerpt":{"rendered":"

1. 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