{"id":4751,"date":"2026-03-03T09:46:50","date_gmt":"2026-03-03T09:46:50","guid":{"rendered":"https:\/\/flj-pcb.com\/?p=4751"},"modified":"2026-03-03T10:04:27","modified_gmt":"2026-03-03T10:04:27","slug":"pcb-stackup-function-and-design-principles-translation","status":"publish","type":"post","link":"https:\/\/flj-pcb.com\/es\/pcb-stackup-function-and-design-principles-translation\/","title":{"rendered":"Mejores pr\u00e1cticas de apilamiento de placas de circuito impreso multicapa para la integridad de la se\u00f1al"},"content":{"rendered":"

1. Definici\u00f3n y cu\u00e1ndo a\u00f1adir capas<\/h2>\n\n\n\n

Para placas multicapa de alta velocidad<\/a>, un dise\u00f1o b\u00e1sico de dos capas a menudo no puede satisfacer las necesidades de calidad de se\u00f1al y densidad de enrutamiento. En ese caso, es necesario a\u00f1adir capas al apilamiento de PCB para satisfacer las necesidades del dise\u00f1o.<\/p>\n\n\n\n

2. Planos positivos (se\u00f1al) y planos negativos (invertidos)<\/h2>\n\n\n\n

Un plano positivo es la capa de se\u00f1al habitual utilizada para el encaminamiento. Las partes visibles son trazas de cobre. En un plano positivo puedes hacer grandes vaciados de cobre y rellenar \u00e1reas con cobre, por ejemplo usando t\u00e9rminos como \u201ctraza\u201d o \u201ccobre\u201d para describir las \u00e1reas de cobre. V\u00e9ase la Figura 8-32.<\/p>\n\n\n\n

\"8-32
8-32 Capa Plana Positiva<\/figcaption><\/figure><\/div>\n\n\n\n

Un plano negativo es lo contrario. Con un plano negativo, por defecto se vierte cobre en toda la capa. Las \u00e1reas de enrutamiento son los recortes. No hay cobre en las l\u00edneas de enrutamiento. Lo que se hace es tallar el cobre y luego establecer las redes para las \u00e1reas talladas. Ver Figura 8-33.<\/p>\n\n\n\n

\"Figure
Figura 8-33 Capa de plano negativo<\/figcaption><\/figure><\/div>\n\n\n\n

3. Divisi\u00f3n de los planos interiores de potencia\/tierra<\/h2>\n\n\n\n

En las versiones antiguas de Protel, los planos de potencia interiores se divid\u00edan mediante una funci\u00f3n \u201cdividir\u201d. En versiones actuales como Altium Designer 19<\/a>, se divide dibujando \u201cl\u00edneas\u201d y se utiliza la tecla de acceso r\u00e1pido \u201cPL\u201d para colocarlas. Las l\u00edneas de divisi\u00f3n no deben ser demasiado finas. Puede elegir 15 mil o m\u00e1s. Cuando vierta el cobre despu\u00e9s de la divisi\u00f3n, dibuje un pol\u00edgono cerrado con la herramienta \u201cl\u00ednea\u201d, luego haga doble clic dentro del pol\u00edgono y establezca la red para el vertido de cobre. V\u00e9ase la figura 8-34.<\/p>\n\n\n\n

\"Figure
Figura 8-34 Doble clic para asignar red<\/figcaption><\/figure><\/div>\n\n\n\n

Tanto los planos positivos como los negativos pueden utilizarse para capas internas de potencia o de masa. Tambi\u00e9n se puede conseguir un plano interior positivo mediante fresado y vertido de cobre. La ventaja de un plano negativo es que se empieza con una gran \u00e1rea de cobre vertido por defecto. A continuaci\u00f3n, puede a\u00f1adir v\u00edas o cambiar el tama\u00f1o de las coladas sin tener que volver a colar toda la capa. Esto ahorra tiempo en el rec\u00e1lculo del cobre vertido. Cuando las capas interiores se utilizan como planos de potencia y de tierra (tambi\u00e9n llamados planos de tierra o planos de retorno), las capas son en su mayor\u00eda grandes coladas de cobre. La ventaja de utilizar planos negativos es evidente en este caso.<\/p>\n\n\n\n

4. Comprender el apilamiento de placas de circuito impreso<\/h2>\n\n\n\n

A medida que se generalizan los circuitos de alta velocidad, aumenta la complejidad de las placas de circuito impreso. Para evitar interferencias el\u00e9ctricas, hay que separar las capas de se\u00f1al de las de alimentaci\u00f3n. Esto lleva al dise\u00f1o de PCB multicapa. Antes de dise\u00f1ar una PCB multicapa, el dise\u00f1ador debe decidir primero la estructura de la placa en funci\u00f3n del tama\u00f1o del circuito, las dimensiones de la placa y los requisitos de compatibilidad electromagn\u00e9tica (EMC). En otras palabras, debe decidir si va a utilizar una placa de 4, 6 o m\u00e1s capas. Esta es la idea b\u00e1sica del dise\u00f1o de placas multicapa.<\/p>\n\n\n\n

Despu\u00e9s de decidir el n\u00famero de capas, el siguiente paso es colocar las capas internas de alimentaci\u00f3n y tierra y decidir c\u00f3mo distribuir los distintos tipos de se\u00f1ales entre esas capas. Esta elecci\u00f3n es la selecci\u00f3n del apilado. La estructura del apilamiento es un factor importante que afecta al rendimiento CEM de las placas de circuito impreso. Un buen dise\u00f1o del apilamiento puede reducir en gran medida las interferencias electromagn\u00e9ticas (EMI) y la diafon\u00eda.<\/a>.<\/p>\n\n\n\n

M\u00e1s capas no siempre es mejor, y menos capas no siempre es mejor. Para elegir un apilamiento multicapa hay que sopesar muchos factores. Desde el punto de vista del trazado, m\u00e1s capas facilitan el trazado. Pero tambi\u00e9n aumentan el coste y la dificultad de fabricaci\u00f3n. En fabricantes<\/a>, La simetr\u00eda del apilamiento es una preocupaci\u00f3n importante durante la fabricaci\u00f3n. Por tanto, el n\u00famero de capas debe equilibrar todas las necesidades.<\/p>\n\n\n\n

Los dise\u00f1adores experimentados suelen hacer una precolocaci\u00f3n de componentes. A continuaci\u00f3n, analizan los cuellos de botella del encaminamiento. Cuentan las necesidades especiales de encaminamiento, como pares diferenciales y redes sensibles. A partir de ah\u00ed, deciden cu\u00e1ntas capas de se\u00f1al son necesarias. A continuaci\u00f3n, deciden el n\u00famero de capas internas de alimentaci\u00f3n\/tierra en funci\u00f3n de los tipos de alimentaci\u00f3n, las necesidades de aislamiento y la supresi\u00f3n de interferencias. Una vez hecho esto, el n\u00famero total de capas de la placa es b\u00e1sicamente fijo.<\/p>\n\n\n\n

5. Apilamientos comunes de PCB<\/h2>\n\n\n\n

Una vez fijado el n\u00famero de capas, el siguiente trabajo es organizar el orden de esas capas. Las figuras 8-35 y 8-36 muestran apilamientos comunes para placas de 4 y 6 capas.<\/p>\n\n\n\n

\n
\n
\"Figure
Figura 8-35 Estructura Com\u00fan de Apilamiento de Tarjetas de 4 Capas<\/figcaption><\/figure><\/div>\n<\/div>\n\n\n\n
\n
\"Figure
Figura 8-36 Estructura com\u00fan de apilamiento de placas de 6 capas<\/figcaption><\/figure>\n<\/div>\n<\/div><\/div>\n\n\n\n

6. An\u00e1lisis de apilamiento<\/h2>\n\n\n\n

\u00bfC\u00f3mo apilar? \u00bfQu\u00e9 apilamiento es mejor? Sigue estas reglas b\u00e1sicas:<\/p>\n\n\n\n

Haga que el lado del componente y el lado de la soldadura sean planos de tierra completos cuando sea posible (esto proporciona apantallamiento).<\/p>\n\n\n\n

Evite en la medida de lo posible las capas de enrutamiento paralelas adyacentes.<\/p>\n\n\n\n

Coloque todas las capas de se\u00f1al junto a un plano de tierra siempre que sea posible.<\/p>\n\n\n\n

Coloque las se\u00f1ales cr\u00edticas junto a una capa de tierra y evite cruzar por zonas divididas.<\/p>\n\n\n\n

Aplique estas reglas a los ejemplos comunes de apilamiento que se muestran en las Figuras 8-35 y 8-36. El an\u00e1lisis es el siguiente.<\/p>\n\n\n\n

(1) La Tabla 8-1 compara los pros y los contras de tres esquemas comunes de apilamiento de placas de 4 capas.<\/p>\n\n\n\n

Esquema<\/th>Esquema (ASCII Art)<\/th>Ventajas<\/th>Desventajas<\/th><\/tr><\/thead>
Esquema 1<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 PWR01 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN02 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Tierra) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Este esquema est\u00e1 dise\u00f1ado principalmente para conseguir un efecto de apantallamiento de una sola capa, con el plano de potencia y el plano de tierra situados en las capas superior e inferior respectivamente.<\/td>(1) Los planos de potencia y tierra est\u00e1n demasiado separados, lo que provoca una impedancia excesiva en el plano de potencia;(2) Los planos de potencia y tierra est\u00e1n muy incompletos debido a la influencia de las zapatas de los componentes y otros factores;(3) El plano de referencia incompleto provoca trazas de se\u00f1al discontinuas, lo que dificulta conseguir el efecto de apantallamiento esperado.<\/td><\/tr>
Esquema 2<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR03 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Se\u00f1al) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Se coloca un plano de tierra bajo el lado del componente, lo que lo hace adecuado para escenarios en los que los componentes principales se colocan en la capa superior o las se\u00f1ales clave se enrutan en la capa superior.<\/td>\/<\/td><\/tr>
Esquema 3<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR02 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND03 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Se\u00f1al) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Similar al esquema 2, es adecuado para escenarios en los que los componentes principales se colocan en la capa inferior o las se\u00f1ales clave se enrutan en la capa inferior.<\/td>\/<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

(2) La Tabla 8-2 compara los pros y los contras de cuatro esquemas comunes de apilamiento de placas de 6 capas.<\/p>\n\n\n\n

Esquema<\/th>Esquema (ASCII Art)<\/th>Ventajas<\/th>Desventajas<\/th><\/tr><\/thead>
Esquema 1<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Se\u00f1al) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Adopta 4 capas de se\u00f1al y dos capas internas de alimentaci\u00f3n\/tierra, lo que proporciona m\u00e1s capas de se\u00f1al para facilitar el enrutamiento entre componentes.<\/td>(1) El plano de potencia y el plano de tierra est\u00e1n demasiado separados, lo que provoca un acoplamiento insuficiente;(2) Las capas de se\u00f1al SIN03 y SIN04 se encaminan principalmente en capas superficiales, lo que provoca un aislamiento deficiente de la se\u00f1al y diafon\u00eda, y requiere un encaminamiento escalonado.<\/td><\/tr>
Esquema 2<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN02 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND03 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR04 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN05 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Se\u00f1al) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>El plano de potencia y el plano de tierra est\u00e1n totalmente acoplados.<\/td>Las capas adyacentes de las capas de se\u00f1al de superficie tambi\u00e9n son capas de se\u00f1al, lo que provoca un aislamiento deficiente de la se\u00f1al y diafon\u00eda.<\/td><\/tr>
Esquema 3<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Se\u00f1al) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>(1) El plano de potencia y el plano de tierra est\u00e1n totalmente acoplados;(2) Cada capa de se\u00f1al est\u00e1 directamente adyacente al plano interno de potencia\/tierra, lo que proporciona un aislamiento eficaz de otras capas de se\u00f1al y reduce la diafon\u00eda;(3) La capa de se\u00f1al SIN03 est\u00e1 adyacente a dos planos internos (GND02 y PWR05), lo que puede blindar eficazmente la interferencia externa en SIN03 y la diafon\u00eda de SIN03 a otras capas.<\/td>\/<\/td><\/tr>
Esquema 4<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Se\u00f1al) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR03 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Tierra) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Alimentaci\u00f3n) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Se\u00f1al) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>(1) El plano de potencia y el plano de tierra est\u00e1n totalmente acoplados;(2) Cada capa de se\u00f1al est\u00e1 directamente adyacente al plano interno de potencia\/tierra, lo que proporciona un aislamiento eficaz de otras capas de se\u00f1al y reduce la diafon\u00eda.<\/td>\/<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Si se comparan los esquemas 1 y 4, cuando el rendimiento de la se\u00f1al es la m\u00e1xima prioridad, los esquemas 3 y 4 son claramente mejores que los dos primeros. Pero en el dise\u00f1o de productos reales, el coste es una preocupaci\u00f3n importante. Con una alta densidad de enrutamiento, los dise\u00f1adores suelen elegir el esquema 1 para el apilamiento con el fin de ahorrar costes. Cuando se utiliza el esquema 1, hay que prestar especial atenci\u00f3n a los cruces entre dos capas de se\u00f1al adyacentes e intentar reducir la diafon\u00eda en la medida de lo posible.<\/p>\n\n\n\n

(3) Para tarjetas comunes de 8 capas, las opciones de apilamiento recomendadas se muestran en la Figura 8-37. Prefiera la opci\u00f3n 1 o la opci\u00f3n 2. La opci\u00f3n 3 es utilizable.<\/p>\n\n\n\n

\"Figure
Figura 8-37 Esquemas de apilamiento recomendados para placas de 8 capas comunes<\/figcaption><\/figure><\/div>\n\n\n\n

7. A\u00f1adir y editar capas<\/h2>\n\n\n\n

Despu\u00e9s de confirmar el plan de apilamiento, \u00bfc\u00f3mo agregar capas en Altium Designer? A continuaci\u00f3n se muestra un ejemplo sencillo.<\/p>\n\n\n\n

Ejecute el comando de men\u00fa \u201cDise\u00f1o \u2192 Gestor de pilas de capas\u201d o pulse la tecla de acceso directo \u201cDK\u201d para abrir el Gestor de pilas de capas. Configure los par\u00e1metros relacionados como se muestra en la Figura 8-38.<\/p>\n\n\n\n

Haga clic con el bot\u00f3n derecho y elija \u201cInsertar capa arriba\u201d o \u201cInsertar capa abajo\u201d para a\u00f1adir una capa. Puede a\u00f1adir un plano positivo o un plano negativo. Utilice \u201cMover capa arriba\u201d o \u201cMover capa abajo\u201d para ajustar el orden de las capas a\u00f1adidas.<\/p>\n\n\n\n

Haga doble clic en el nombre de la capa para cambiarle el nombre. Puedes nombrar las capas TOP, GND02, SIN03, SIN04, PWR05, BOTTOM, etc. Altium Designer 19 soporta esta nomenclatura \u201cletra + n\u00famero de capa\u201d. Esto facilita la lectura y el reconocimiento.<\/p>\n\n\n\n

Ajuste el grosor del tablero y de las capas seg\u00fan el apilado.<\/p>\n\n\n\n

Para cumplir el requisito de 20H del dise\u00f1o, puede establecer la cantidad de retenci\u00f3n del plano negativo (desplazamiento interior). [Nota: el texto original utiliza \u201c20H\u201d. El traductor mantiene este t\u00e9rmino tal como est\u00e1 escrito].<\/p>\n\n\n\n

Haga clic en \u201cAceptar\u201d para finalizar los ajustes de apilamiento. En la Figura 8-39 se muestra un ejemplo de efecto de apilamiento de una tarjeta de 4 capas.<\/p>\n\n\n\n

\"Figure
Figura 8-39 Resultado del apilado de la placa de 4 capas<\/figcaption><\/figure><\/div>\n\n\n\n

8. Recomendaci\u00f3n<\/h2>\n\n\n\n

Se sugiere tratar las capas de se\u00f1al como planos positivos y tratar las capas de potencia y tierra como planos negativos. Este enfoque puede reducir en gran medida el tama\u00f1o de los datos del archivo y acelerar el trabajo de dise\u00f1o.<\/p>","protected":false},"excerpt":{"rendered":"

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