{"id":4751,"date":"2026-03-03T09:46:50","date_gmt":"2026-03-03T09:46:50","guid":{"rendered":"https:\/\/flj-pcb.com\/?p=4751"},"modified":"2026-03-03T10:04:27","modified_gmt":"2026-03-03T10:04:27","slug":"pcb-stackup-function-and-design-principles-translation","status":"publish","type":"post","link":"https:\/\/flj-pcb.com\/fi\/pcb-stackup-function-and-design-principles-translation\/","title":{"rendered":"Monikerroksinen PCB Stackup parhaat k\u00e4yt\u00e4nn\u00f6t signaalin eheytt\u00e4 varten"},"content":{"rendered":"

1. M\u00e4\u00e4ritelm\u00e4 ja kerrosten lis\u00e4\u00e4minen<\/h2>\n\n\n\n

Osoitteessa nopeat monikerroslevyt<\/a>, kaksikerroksinen perussuunnittelu ei useinkaan pysty t\u00e4ytt\u00e4m\u00e4\u00e4n signaalin laadun ja reititystiheyden tarpeita. T\u00e4ll\u00f6in sinun on lis\u00e4tt\u00e4v\u00e4 kerroksia piirilevyn pinoamiseen suunnittelun tarpeiden t\u00e4ytt\u00e4miseksi.<\/p>\n\n\n\n

2. Positiiviset (signaali) tasot ja negatiiviset (k\u00e4\u00e4nteiset) tasot.<\/h2>\n\n\n\n

Positiivinen taso on tavallinen signaalikerros, jota k\u00e4ytet\u00e4\u00e4n reititykseen. N\u00e4kyv\u00e4t osat ovat kuparij\u00e4lki\u00e4. Positiiviselle tasolle voi tehd\u00e4 suuria kuparivaluja ja t\u00e4ytt\u00e4\u00e4 alueita kuparilla, jolloin kuparialueita kuvaavat esimerkiksi termit \u201ctrace\u201d tai \u201ccopper\u201d. Katso kuva 8-32.<\/p>\n\n\n\n

\"8-32
8-32 Positiivinen tasokerros<\/figcaption><\/figure><\/div>\n\n\n\n

Negatiivinen taso on p\u00e4invastainen. Negatiivisessa tasossa oletusarvoisesti kuparia valetaan koko kerroksen yli. Reititysalueet ovat leikkauksia. Reitityslinjoissa ei ole kuparia. Sin\u00e4 kaiverrat kuparia ja asetat sitten verkot kaiverretuille alueille. Katso kuva 8-33.<\/p>\n\n\n\n

\"Figure
Kuva 8-33 Negatiivinen tasokerros<\/figcaption><\/figure><\/div>\n\n\n\n

3. Sis\u00e4isten teho-\/maatasojen jakaminen<\/h2>\n\n\n\n

Vanhemmissa Protel-versioissa sis\u00e4iset tehotasot jaettiin \u201csplit\u201d-toiminnolla. Nykyisiss\u00e4 versioissa, kuten Altium Designer 19<\/a>, jaat piirt\u00e4m\u00e4ll\u00e4 \u201cviivoja\u201d ja k\u00e4ytt\u00e4m\u00e4ll\u00e4 pikan\u00e4pp\u00e4int\u00e4 \u201cPL\u201d niiden sijoittamiseen. Jaetut viivat eiv\u00e4t saa olla liian ohuita. Voit valita 15 mil tai suuremman. Kun kaadat kuparia halkaisun j\u00e4lkeen, piirr\u00e4 suljettu monikulmio \u201cviiva\u201d-ty\u00f6kalulla, kaksoisnapsauta sitten monikulmion sis\u00e4ll\u00e4 ja aseta verkko kuparivalua varten. Katso kuva 8-34.<\/p>\n\n\n\n

\"Figure
Kuva 8-34 Kaksoisnapsautus verkon osoittamiseksi<\/figcaption><\/figure><\/div>\n\n\n\n

Sek\u00e4 positiivisia ett\u00e4 negatiivisia tasoja voidaan k\u00e4ytt\u00e4\u00e4 sis\u00e4isi\u00e4 teho- tai maakerroksia varten. Positiivinen sis\u00e4taso voidaan saavuttaa my\u00f6s reititt\u00e4m\u00e4ll\u00e4 ja kuparivaluilla. Negatiivisen tason etuna on se, ett\u00e4 oletusarvoisesti aloitat suurella valetulla kuparialueella. Sen j\u00e4lkeen voit lis\u00e4t\u00e4 l\u00e4pivientej\u00e4 tai muuttaa valukokoja ilman, ett\u00e4 koko kerros valetaan uudelleen. T\u00e4m\u00e4 s\u00e4\u00e4st\u00e4\u00e4 aikaa kuparivalun uudelleenlaskennassa. Kun sis\u00e4isi\u00e4 kerroksia k\u00e4ytet\u00e4\u00e4n virta- ja maatasoina (joita kutsutaan my\u00f6s maatasoksi tai paluutasoksi), kerrokset ovat useimmiten suuria kuparivaluja. Negatiivisten tasojen k\u00e4yt\u00f6n etu on t\u00e4ss\u00e4 selv\u00e4.<\/p>\n\n\n\n

4. PCB Stackupin ymm\u00e4rt\u00e4minen<\/h2>\n\n\n\n

Kun nopeat piirit yleistyv\u00e4t, piirilevyjen monimutkaisuus kasvaa. S\u00e4hk\u00f6isten h\u00e4iri\u00f6iden v\u00e4ltt\u00e4miseksi signaalikerrokset ja tehokerrokset on erotettava toisistaan. T\u00e4m\u00e4 johtaa monikerroksiseen PCB-suunnitteluun. Ennen monikerroksisen piirilevyn suunnittelua suunnittelijan on ensin p\u00e4\u00e4tett\u00e4v\u00e4 levyn rakenne piirin koon, levyn mittojen ja s\u00e4hk\u00f6magneettisen yhteensopivuuden (EMC) vaatimusten perusteella. Toisin sanoen on p\u00e4\u00e4tett\u00e4v\u00e4, k\u00e4ytet\u00e4\u00e4nk\u00f6 4-, 6- vai useampikerroksista levy\u00e4. T\u00e4m\u00e4 on monikerroksisen levyn suunnittelun perusajatus.<\/p>\n\n\n\n

Kun kerrosten lukum\u00e4\u00e4r\u00e4 on p\u00e4\u00e4tetty, seuraava vaihe on sijoittaa sis\u00e4iset virta- ja maakerrokset ja p\u00e4\u00e4tt\u00e4\u00e4, miten eri signaalityypit jaetaan n\u00e4ille kerroksille. T\u00e4m\u00e4 valinta on pinoamisvalinta. Pinoamisrakenne on t\u00e4rke\u00e4 tekij\u00e4, joka vaikuttaa piirilevyn EMC-suorituskykyyn. Hyv\u00e4 p\u00e4\u00e4llekk\u00e4issuunnittelu voi v\u00e4hent\u00e4\u00e4 huomattavasti s\u00e4hk\u00f6magneettisia h\u00e4iri\u00f6it\u00e4 (EMI) ja ristikk\u00e4isviestint\u00e4\u00e4.<\/a>.<\/p>\n\n\n\n

Enemm\u00e4n kerroksia ei ole aina parempi, eik\u00e4 v\u00e4hemm\u00e4n kerroksia ole aina parempi. Monikerroksisen kerroskokonaisuuden valitseminen edellytt\u00e4\u00e4 monien tekij\u00f6iden punnitsemista. Reitityksen kannalta useampi kerros helpottaa reitityst\u00e4. Mutta my\u00f6s valmistuskustannukset ja -vaikeudet nousevat. Osoitteessa valmistajat<\/a>, onko pinoaminen symmetrinen, on t\u00e4rke\u00e4 huolenaihe valmistuksen aikana. Kerrosluvun on siis oltava tasapainossa kaikkien tarpeiden kanssa.<\/p>\n\n\n\n

Kokeneet suunnittelijat tekev\u00e4t yleens\u00e4 komponenttien esisijoittelun. Sitten he analysoivat reitityksen pullonkaulat. He laskevat erityiset reititystarpeet, kuten differentiaaliparit ja herk\u00e4t verkot. T\u00e4m\u00e4n perusteella he p\u00e4\u00e4tt\u00e4v\u00e4t, kuinka monta signaalikerrosta tarvitaan. Sen j\u00e4lkeen he p\u00e4\u00e4tt\u00e4v\u00e4t sis\u00e4isten teho-\/maakerrosten m\u00e4\u00e4r\u00e4n tehotyyppien, eristystarpeiden ja h\u00e4iri\u00f6npoiston perusteella. T\u00e4m\u00e4n j\u00e4lkeen levykerrosten kokonaism\u00e4\u00e4r\u00e4 on periaatteessa kiinte\u00e4.<\/p>\n\n\n\n

5. Yleiset PCB Stackups<\/h2>\n\n\n\n

Kun kerrosten lukum\u00e4\u00e4r\u00e4 on m\u00e4\u00e4ritetty, seuraava teht\u00e4v\u00e4 on j\u00e4rjest\u00e4\u00e4 kerrosten j\u00e4rjestys. Kuvissa 8-35 ja 8-36 on esitetty 4- ja 6-kerroksisten piirilevyjen tavanomaiset pinoamisj\u00e4rjestykset.<\/p>\n\n\n\n

\n
\n
\"Figure
Kuva 8-35 Yleinen 4-kerroksisen piirilevyn pinoamisrakenne<\/figcaption><\/figure><\/div>\n<\/div>\n\n\n\n
\n
\"Figure
Kuva 8-36 Yleinen 6-kerroksisen piirilevyn pinoamisrakenne<\/figcaption><\/figure>\n<\/div>\n<\/div><\/div>\n\n\n\n

6. Pinoamisanalyysi<\/h2>\n\n\n\n

Miten pinota? Mik\u00e4 pinoaminen on parempi? Noudata n\u00e4it\u00e4 peruss\u00e4\u00e4nt\u00f6j\u00e4:<\/p>\n\n\n\n

Tee komponenttipuolen ja juotospuolen maadoitukset mahdollisuuksien mukaan t\u00e4ysiksi maadoitustasoiksi (t\u00e4m\u00e4 antaa suojauksen).<\/p>\n\n\n\n

V\u00e4lt\u00e4 vierekk\u00e4isi\u00e4 rinnakkaisia reitityskerroksia niin paljon kuin mahdollista.<\/p>\n\n\n\n

Aseta kaikki signaalikerrokset maatason viereen, jos mahdollista.<\/p>\n\n\n\n

Aseta kriittiset signaalit maadoituskerroksen viereen ja v\u00e4lt\u00e4 jaettujen alueiden ylitt\u00e4mist\u00e4.<\/p>\n\n\n\n

Sovella n\u00e4it\u00e4 s\u00e4\u00e4nt\u00f6j\u00e4 kuvissa 8-35 ja 8-36 esitettyihin yleisiin pinoamisesimerkkeihin. Analyysi on seuraava.<\/p>\n\n\n\n

(1) Taulukossa 8-1 verrataan kolmen yleisen 4-kerroksisen piirilevyn kasausj\u00e4rjestelm\u00e4n etuja ja haittoja.<\/p>\n\n\n\n

J\u00e4rjestelm\u00e4<\/th>Kaavio (ASCII Art)<\/th>Edut<\/th>Haitat<\/th><\/tr><\/thead>
Kaavio 1<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 PWR01 (Virta) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN02 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Maa) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>T\u00e4m\u00e4 j\u00e4rjestelm\u00e4 on suunniteltu p\u00e4\u00e4asiassa yhden kerroksen suojausvaikutuksen aikaansaamiseksi, kun tehotasot ja maatasot on sijoitettu vastaavasti yl\u00e4- ja alakerroksiin.<\/td>(1) Teho- ja maatasot ovat liian kaukana toisistaan, mik\u00e4 johtaa liialliseen impedanssiin tehotasossa;(2) Teho- ja maatasot ovat eritt\u00e4in ep\u00e4t\u00e4ydellisi\u00e4 komponenttityynyjen ja muiden tekij\u00f6iden vaikutuksesta;(3) Ep\u00e4t\u00e4ydellinen vertailutaso aiheuttaa ep\u00e4jatkuvia signaalij\u00e4lki\u00e4, mik\u00e4 vaikeuttaa odotetun suojausvaikutuksen saavuttamista.<\/td><\/tr>
Kaavio 2<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR03 (Virta) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Signaali) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Komponenttipuolen alle on sijoitettu maataso, joten se soveltuu skenaarioihin, joissa p\u00e4\u00e4komponentit on sijoitettu p\u00e4\u00e4llimm\u00e4iseen kerrokseen tai t\u00e4rkeimm\u00e4t signaalit on reititetty p\u00e4\u00e4llimm\u00e4iseen kerrokseen.<\/td>\/<\/td><\/tr>
Kaavio 3<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR02 (Virta) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND03 (Maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Signaali) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Samoin kuin j\u00e4rjestelm\u00e4 2, se soveltuu skenaarioihin, joissa p\u00e4\u00e4komponentit on sijoitettu alimpaan kerrokseen tai keskeiset signaalit on reititetty alimpaan kerrokseen.<\/td>\/<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

(2) Taulukossa 8-2 verrataan nelj\u00e4n yleisen 6-kerroksisen levyn kasausj\u00e4rjestelm\u00e4n etuja ja haittoja.<\/p>\n\n\n\n

J\u00e4rjestelm\u00e4<\/th>Kaavio (ASCII Art)<\/th>Edut<\/th>Haitat<\/th><\/tr><\/thead>
Kaavio 1<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN04 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Virta) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signaali) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Ottaa k\u00e4ytt\u00f6\u00f6n 4 signaalikerrosta ja kaksi sis\u00e4ist\u00e4 virta\/maakerrosta, mik\u00e4 tarjoaa enemm\u00e4n signaalikerroksia komponenttien v\u00e4lisen reitityksen helpottamiseksi.<\/td>(1) Tehotaso ja maataso ovat liian kaukana toisistaan, mik\u00e4 johtaa riitt\u00e4m\u00e4tt\u00f6m\u00e4\u00e4n kytkent\u00e4\u00e4n; (2) Signaalikerrokset SIN03 ja SIN04 reititet\u00e4\u00e4n p\u00e4\u00e4asiassa pintakerroksissa, mik\u00e4 johtaa huonoon signaalieristykseen ja ristikk\u00e4isviestint\u00e4\u00e4n, mik\u00e4 edellytt\u00e4\u00e4 porrastettua reitityst\u00e4.<\/td><\/tr>
Kaavio 2<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN02 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND03 (Maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR04 (Virta) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN05 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signaali) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>Tehotaso ja maataso ovat t\u00e4ysin kytkettyj\u00e4.<\/td>Pintasignaalikerrosten viereiset kerrokset ovat my\u00f6s signaalikerroksia, mik\u00e4 johtaa huonoon signaalieristykseen ja ristikk\u00e4isviestint\u00e4\u00e4n.<\/td><\/tr>
Kaavio 3<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN03 (signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Teho) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signaali) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>(1) Tehotaso ja maataso ovat t\u00e4ysin kytkettyj\u00e4;(2) Kukin signaalikerros on suoraan sis\u00e4isen teho\/maatason vieress\u00e4, mik\u00e4 tarjoaa tehokkaan eristyksen muista signaalikerroksista ja v\u00e4hent\u00e4\u00e4 ristikk\u00e4isviestint\u00e4\u00e4;(3) Signaalikerros SIN03 on kahden sis\u00e4isen tason (GND02 ja PWR05) vieress\u00e4, mik\u00e4 voi tehokkaasti suojata ulkoisia h\u00e4iri\u00f6it\u00e4 SIN03:ssa ja ristikk\u00e4isviestint\u00e4\u00e4 SIN03:sta muihin kerroksiin.<\/td>\/<\/td><\/tr>
Kaavio 4<\/strong><\/td>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 SIN01 (Signaali) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND02 (Maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR03 (Virta) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 GND04 (Maa) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 PWR05 (Teho) \u2502 \u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524 \u2502 SIN06 (Signaali) \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/code><\/td>(1) Tehotaso ja maataso ovat t\u00e4ysin kytkettyj\u00e4;(2) Kukin signaalikerros on suoraan sis\u00e4isen teho-\/maatasotason vieress\u00e4, mik\u00e4 tarjoaa tehokkaan eristyksen muista signaalikerroksista ja v\u00e4hent\u00e4\u00e4 ristikk\u00e4isviestint\u00e4\u00e4.<\/td>\/<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

J\u00e4rjestelmien 1 ja 4 vertailun perusteella voidaan todeta, ett\u00e4 kun signaalin suorituskyky on t\u00e4rkein prioriteetti, j\u00e4rjestelm\u00e4t 3 ja 4 ovat selv\u00e4sti parempia kuin kaksi ensimm\u00e4ist\u00e4 j\u00e4rjestelm\u00e4\u00e4. Todellisessa tuotesuunnittelussa kustannukset ovat kuitenkin merkitt\u00e4v\u00e4 huolenaihe. Kun reititystiheys on suuri, suunnittelijat valitsevat usein j\u00e4rjestelm\u00e4n 1 pinoamista varten kustannusten s\u00e4\u00e4st\u00e4miseksi. Kun reitit\u00e4t j\u00e4rjestelm\u00e4\u00e4 1, kiinnit\u00e4 erityist\u00e4 huomiota kahden vierekk\u00e4isen signaalikerroksen v\u00e4lisiin risteyksiin ja yrit\u00e4 v\u00e4hent\u00e4\u00e4 ristikk\u00e4isviestint\u00e4\u00e4 mahdollisimman paljon.<\/p>\n\n\n\n

(3) Yleisten 8-kerroksisten piirilevyjen suositellut pinoutumisvaihtoehdot on esitetty kuvassa 8-37. Suosi vaihtoehtoa 1 tai 2. Vaihtoehto 3 on k\u00e4ytt\u00f6kelpoinen.<\/p>\n\n\n\n

\"Figure
Kuva 8-37 Suositeltavat pinontasuunnitelmat yleisimmille 8-kerroksisille piirilevyille.<\/figcaption><\/figure><\/div>\n\n\n\n

7. Tasojen lis\u00e4\u00e4minen ja muokkaaminen<\/h2>\n\n\n\n

Kun olet vahvistanut pinoamissuunnitelman, miten lis\u00e4\u00e4t kerrokset Altium Designerissa? Seuraavassa on yksinkertainen esimerkki.<\/p>\n\n\n\n

Avaa Layer Stack Manager valikkokomennolla \u201cDesign \u2192 Layer Stack Manager\u201d tai painamalla pikan\u00e4pp\u00e4int\u00e4 \u201cDK\u201d. Aseta asiaan liittyv\u00e4t parametrit kuvan 8-38 mukaisesti.<\/p>\n\n\n\n

Napsauta hiiren kakkospainikkeella ja valitse \u201cLis\u00e4\u00e4 kerros yl\u00e4puolelle\u201d tai \u201cLis\u00e4\u00e4 kerros alapuolelle\u201d lis\u00e4t\u00e4ksesi kerroksen. Voit lis\u00e4t\u00e4 positiivisen tason tai negatiivisen tason. K\u00e4yt\u00e4 \u201cSiirr\u00e4 taso yl\u00f6s\u201d tai \u201cSiirr\u00e4 taso alas\u201d, kun haluat s\u00e4\u00e4t\u00e4\u00e4 lis\u00e4ttyjen tasojen j\u00e4rjestyst\u00e4.<\/p>\n\n\n\n

Nime\u00e4 kerros uudelleen kaksoisnapsauttamalla sen nime\u00e4. Voit nimet\u00e4 kerrokset TOP, GND02, SIN03, SIN04, PWR05, BOTTOM jne. Altium Designer 19 tukee t\u00e4t\u00e4 \u201ckirjain + kerroksen numero\u201d nime\u00e4mist\u00e4. T\u00e4m\u00e4 helpottaa lukemista ja tunnistamista.<\/p>\n\n\n\n

Aseta levyn ja kerroksen paksuus pinoamisen mukaan.<\/p>\n\n\n\n

Voit asettaa negatiivisen tason pid\u00e4ttymism\u00e4\u00e4r\u00e4n (sis\u00e4inen siirtym\u00e4), jos haluat t\u00e4ytt\u00e4\u00e4 suunnittelun 20H-vaatimuksen. [Huomautus: alkuper\u00e4isess\u00e4 tekstiss\u00e4 k\u00e4ytet\u00e4\u00e4n \u201c20H\u201d. K\u00e4\u00e4nt\u00e4j\u00e4 pit\u00e4\u00e4 t\u00e4m\u00e4n termin kirjoitettuna.]<\/p>\n\n\n\n

Napsauta \u201cOK\u201d viimeistell\u00e4ksesi pinoamisasetukset. Esimerkki 4-kerroksisen piirilevyn pinoamisvaikutuksesta on esitetty kuvassa 8-39.<\/p>\n\n\n\n

\"Figure
Kuva 8-39 4-kerroksisen piirilevyn pinoamistulos<\/figcaption><\/figure><\/div>\n\n\n\n

8. Suositus<\/h2>\n\n\n\n

Signaalikerroksia ehdotetaan k\u00e4sitelt\u00e4v\u00e4n positiivisina tasoina ja teho- ja maakerroksia negatiivisina tasoina. T\u00e4m\u00e4 l\u00e4hestymistapa voi v\u00e4hent\u00e4\u00e4 huomattavasti tiedoston datakokoa ja nopeuttaa suunnitteluty\u00f6t\u00e4.<\/p>","protected":false},"excerpt":{"rendered":"

1. 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