With the advent of the information age, the use of pcb boards is becoming more and more extensive, and the development of pcb boards is becoming more and more complex. As electronic components are arranged more and more densely on the PCB, electrical interference has become an inevitable problem. In the design and application of multi-layer boards, the signal layer and the power layer must be separated, so the design and arrangement of the stack is particularly important. A good design scheme can greatly reduce the influence of EMI and crosstalk in multilayer boards.
Compared with ordinary single-layer boards, the design of multi-layer boards adds signal layers, wiring layers, and arranges independent power layers and ground layers. The advantages of multi-layer boards are mainly reflected in providing a stable voltage for digital signal conversion, and evenly adding power to each component at the same time, effectively reducing the interference between signals.
The power supply is used in a large area of copper laying and the ground layer, which can greatly reduce the resistance of the power layer and the ground layer, so that the voltage on the power layer is stable, and the characteristics of each signal line can be guaranteed, which is very beneficial to impedance and crosstalk reduction. In the design of high-end circuit boards, it has been clearly stipulated that more than 60% of the stacking schemes should be used. Multi-layer boards, electrical characteristics, and suppression of electromagnetic radiation all have incomparable advantages over low-layer boards. In terms of cost, generally speaking, the more layers there are, the more expensive the price is, because the cost of the PCB board is related to the number of layers, and the density per unit area. After reducing the number of layers, the wiring space will be reduced, thereby increasing the wiring density. , and even meet the design requirements by reducing the line width and distance. These may increase costs appropriately. It is possible to reduce the stacking and reduce the cost, but it makes the electrical performance worse. This kind of design is usually counterproductive.
Looking at the PCB microstrip wiring on the model, the ground layer can also be regarded as a part of the transmission line. The ground copper layer can be used as a signal line loop path. The power plane is connected to the ground plane through a decoupling capacitor, in the case of AC. Both are equivalent. The difference between low frequency and high frequency current loops is that. At low frequencies, the return current follows the path of least resistance. At high frequencies, the return current is along the path of least inductance. The current returns, concentrated and distributed directly below the signal traces.
In the case of high frequency, if a wire is directly laid on the ground layer, even if there are more loops, the current return will flow back to the signal source from the wiring layer under the originating path. Because this path has the least impedance. This kind of use of large capacitive coupling to suppress the electric field, and the minimum capacitive coupling to suppress the magnetic plant to maintain low reactance, we call it self-shielding.
It can be seen from the formula that when the current flows back, the distance from the signal line is inversely proportional to the current density. This minimizes the loop area and inductance. At the same time, it can be concluded that if the distance between the signal line and the loop is close, the currents of the two are similar in magnitude and opposite in direction. And the magnetic field generated by the external space can be offset, so the external EMI is also very small. In the stack design, it is best to have each signal trace correspond to a very close ground layer.
In the problem of crosstalk on the ground layer, the crosstalk caused by high-frequency circuits is mainly due to inductive coupling. From the above current loop formula, it can be concluded that the loop currents generated by the two signal lines close together will overlap. So there will be magnetic interference.
K in the formula is related to the signal rise time and the length of the interference signal line. In the stack setting, shortening the distance between the signal layer and the ground layer will effectively reduce the interference from the ground layer. When laying copper on the power supply layer and the ground layer on the PCB wiring, a separation wall will appear in the copper laying area if you do not pay attention. The occurrence of this kind of problem is most likely due to the high density of via holes, or the unreasonable design of the via isolation area. This slows down the rise time and increases the loop area. Inductance increases and creates crosstalk and EMI.
We should try our best to set up the shop heads in pairs. This is in consideration of the balance structure requirements in the process, because the unbalanced structure may cause the deformation of the pcb board. For each signal layer, it is best to have an ordinary city as an interval. The distance between the high-end power supply and the copper city is conducive to stability and reduction of EMI. In high-speed board design, redundant ground planes can be added to isolate signal planes.
Post time: Mar-23-2023