{"id":4132,"date":"2025-10-21T06:59:15","date_gmt":"2025-10-21T06:59:15","guid":{"rendered":"https:\/\/flj-pcb.com\/?p=4132"},"modified":"2025-10-21T07:03:01","modified_gmt":"2025-10-21T07:03:01","slug":"three-levels-of-routing-in-pcb-design","status":"publish","type":"post","link":"https:\/\/flj-pcb.com\/vi\/three-levels-of-routing-in-pcb-design\/","title":{"rendered":"Ba c\u1ea5p \u0111\u1ed9 \u0111\u1ecbnh tuy\u1ebfn trong thi\u1ebft k\u1ebf m\u1ea1ch in (PCB)"},"content":{"rendered":"

In PCB design, routing can be seen in three broad levels. The first level is basic connectivity. This is the most basic demand in PCB design. If the nets do not connect, the board has no fundamental function. Then the board is a scrap. Do not talk about other things.<\/p>\n\n\n\n

The second level is performance. This is the measure of how good a printed circuit board is. After routing, we must think about how to reach the best performance. We must avoid different kinds of interference. We must also keep signals stable and clean.<\/p>\n\n\n\n

The third level is appearance. The traces may connect and the board may show good electrical performance, but the layout can still look messy. In that case, we should make the routing look neat. Neat routing helps later testing and repair. Neat routing also shows the skills of a senior engineer.<\/p>\n\n\n\n

How to route well<\/h2>\n\n\n\n

Routing methods can vary a lot. To avoid problems such as reflected signals when input and output traces run close and parallel, and to avoid parasitic coupling when traces on two adjacent layers run parallel, we must think about many factors. If interference is strong enough, the board may not work at all. Below are some recommended rules for PCB routing.The “five-five” rule (layer choice rule)<\/p>\n\n\n\n

This rule helps choose the number of PCB layers. When the clock frequency reaches 5 MHz or the pulse rise time is less than 5 ns, the PCB should be a multilayer board. This is a common rule.<\/p>\n\n\n\n

Sometimes people still choose a two-layer board due to cost. If you use two layers, try to use one full side as a solid ground plane. That helps performance.<\/p>\n\n\n\n

Mixed digital and analog ground rules<\/h3>\n\n\n\n

Now many PCBs have both digital and analog circuits. When routing, think about interference between them, especially noise on the ground. Digital circuits work at high frequency. Analog circuits are often sensitive.<\/p>\n\n\n\n

For signals, keep high-frequency traces far from sensitive analog parts. For ground, the whole PCB has one node to the outside world. So you must treat digital and analog grounding inside the board carefully.<\/p>\n\n\n\n

Inside the board, digital ground and analog ground are often separate and not connected to each other. They only join at the point where the PCB connects to the outside world, such as a connector. Make sure digital ground and analog ground have a short link at a single point. Some systems may choose not to share ground on the board. Follow the system design decision.<\/p>\n\n\n\n

Handling component leads in large copper areas<\/h3>\n\n\n\n

Large copper ground or power areas often meet many component leads. For handling part leads we must balance electric performance and assembly.<\/p>\n\n\n\n

From an electrical view, a pad should be fully connected to copper for best performance. But full copper pads create problems in soldering. Problems include:<\/p>\n\n\n\n

Soldering needs a lot of heat from the soldering iron.<\/p>\n\n\n\n

It is easier to get cold or weak solder joints.<\/p>\n\n\n\n

To balance electrical needs and manufacturing, make thermal relief pads. A common form is a cross-shaped pad. This is called thermal relief or thermal pad. It helps soldering by isolating the pad thermally from large copper planes. Thermal pads reduce the chance of cold solder joints. Treat vias connecting to power and ground layers the same way in a multilayer board.<\/p>\n\n\n\n

Grid system rules<\/h3>\n\n\n\n

A grid ground system or mesh ground helps reduce trace inductance and gives a good return path for RF currents. But be careful with grid density.<\/p>\n\n\n\n

If the grid is too dense, there will be many small mesh steps. That generates a lot of layout data. This needs more storage and slows CAD tools. Also some grid paths are useless because they are taken by component pads or mounting holes. If the grid is too sparse, routing becomes hard and routing success falls.<\/p>\n\n\n\n

So choose a reasonable grid density. Standard component lead spacing is 0.1 inch (2.54 mm). So a base grid of 0.1 inch or a neat submultiple is common. Examples: 0.05 inch, 0.025 inch, 0.02 inch, and so on.<\/p>\n\n\n\n

How to check after routing<\/h2>\n\n\n\n

After finishing PCB routing, check whether the design follows the rules and whether it meets manufacturing limits. The checks below are common.<\/p>\n\n\n\n

Areas to check include: general PCB design drawing items, PCB electrical checks, PCB physical checks, mechanical design factors, PCB mounting requirements, board breakout needs, mechanical considerations, electrical concerns, routing paths and placement, trace widths and thickness, trace spacing, trace shape checks, and a list of design items.<\/p>\n\n\n\n

Practical checklist<\/h3>\n\n\n\n

Check if the distance between vias is reasonable.<\/p>\n\n\n\n

Check if power and ground trace widths suit current needs.<\/p>\n\n\n\n

Check whether key signal traces use the best measures (short path, controlled impedance, shielding).<\/p>\n\n\n\n

Check whether analog and digital parts have separate grounds if needed.<\/p>\n\n\n\n

Check whether added copper patterns on the board could short signals.<\/p>\n\n\n\n

Check whether the board has required fabrication lines or markings for the factory.<\/p>\n\n\n\n

Check whether the power and ground plane edges in a multilayer board have the required inset.<\/p>\n\n\n\n

Routing case study and key rules<\/h2>\n\n\n\n

Routing is a major part of PCB design. Routing often takes the most time. Engineers should follow basic rules when routing, such as chamfer rules and the 3W rule.<\/p>\n\n\n\n

Ground loop rule<\/h3>\n\n\n\n

The smallest loop rule means the area enclosed by a signal and its return path should be as small as possible. The smaller the loop area, the less the board will radiate and the less it will receive external noise.<\/p>\n\n\n\n

When splitting ground planes, think about how the plane shape and important signal paths align. Prevent problems from ground plane slots that increase loop area.<\/p>\n\n\n\n

On two-layer designs, keep enough area for power. Fill other space with reference ground copper. Add necessary ground vias to connect the two sides of the board. For key signals, use ground isolation. For high-frequency designs, use multilayer boards.<\/p>\n\n\n\n

\"Ground<\/figure>\n\n\n\n

Shielding and protection rule<\/h3>\n\n\n\n

Shielding is another way to reduce loop area and lower radiation. Use shielding for important signals such as clock and sync signals.<\/p>\n\n\n\n

For very critical or very high-frequency signals, you can use a copper shield or coax-like design. Surround the routed trace on all sides with ground. Also plan how the shield ground connects to the main ground plane.<\/p>\n\n\n\n

\"Shielding<\/figure>\n\n\n\n

Crosstalk control rule<\/h3>\n\n\n\n

Crosstalk means interference between different nets on the PCB. It comes from long parallel routing. The cause is distributed capacitance and inductance between parallel traces.<\/p>\n\n\n\n

Main ways to fight crosstalk:\u2022 Increase spacing between parallel traces. Follow the 3W rule.\u2022 Insert grounded guard traces between critical parallel traces.\u2022 Reduce the distance between the routing layer and the ground plane.<\/p>\n\n\n\n

3W rule reminder<\/h3>\n\n\n\n

To cut crosstalk, keep trace spacing large. If the center distance is three times the trace width, about 70% of the field is isolated. For 98% isolation, use 10W.<\/p>\n\n\n\n

\"3w<\/figure>\n\n\n\n

Direction control of traces<\/h3>\n\n\n\n

Keep the direction of adjacent layers orthogonal. Avoid running traces in the same direction on adjacent layers. This reduces layer-to-layer coupling. If board structure forces parallel runs, especially in high-speed designs, use ground planes between routing layers to isolate them. Also use grounded guard traces between signal traces.<\/p>\n\n\n\n

\"Trace<\/figure>\n\n\n\n

Dangling trace check rule<\/h3>\n\n\n\n

Do not leave any net end floating without connection. Floating traces can act as antennas. They cause extra radiation and they can pick up noise. Avoid this.<\/p>\n\n\n\n

\"Dangling<\/figure>\n\n\n\n

Closed loop check rule<\/h3>\n\n\n\n

Prevent a signal from forming a loop across different layers. In multilayer boards, loops cause radiation. Watch for this and adjust routing.<\/p>\n\n\n\n

\"Closed-loop<\/figure>\n\n\n\n

Chamfer rule<\/h3>\n\n\n\n

Avoid acute or sharp angles in trace corners. Sharp corners can cause unwanted radiation. They can also be poor for manufacturing. Use gentle turns or 45-degree angles.<\/p>\n\n\n\n

\"Chamfer<\/figure>\n\n\n\n

Decoupling components rule<\/h3>\n\n\n\n

Add decoupling capacitors as needed. Decoupling filters noise on the power lines. Place the decoupling capacitor close to the device power pin after the power filter.<\/p>\n\n\n\n

\"Component<\/figure>\n\n\n\n

Integrity of power and ground planes<\/h3>\n\n\n\n

In areas with many vias, do not let vias cut the plane so that the plane separates into smaller parts. Plane splits raise loop area and cause signal return path problems. When you fanout, keep via spacing so that you can still route at least one trace between vias.<\/p>\n\n\n\n

\"Power<\/figure>\n\n\n\n

Power plane overlap rule<\/h3>\n\n\n\n

Avoid overlap of different power planes in space. This reduces interference between supplies, especially when different supplies have large voltage differences. If overlap is unavoidable, consider adding a ground layer between them.<\/p>\n\n\n\n

\"Power<\/figure>\n\n\n\n

20H rule repeated<\/h3>\n\n\n\n

Remember the edge effect. Power to ground plane spacing affects edge radiation. Inset the power plane to keep the field inside the ground plane. An inset of 20H limits about 70% of the field. An inset of 100H limits about 98% of the field.<\/p>\n\n\n\n

\"20H<\/figure>\n\n\n\n

More detailed routing rules and checks<\/h2>\n\n\n\n

Return path control<\/h3>\n\n\n\n

Always plan the signal return path. A signal must have a low-impedance return beneath it. Keep ground return paths short.<\/p>\n\n\n\n

Fanout and via planning<\/h3>\n\n\n\n

For dense BGA or fine pitch parts, plan fanout early. Keep via spacing that leaves room to route signals. For fanout, use microvias or blind vias if needed in advanced designs.<\/p>\n\n\n\n

Impedance control<\/h3>\n\n\n\n

For high-speed single-ended traces or differential pairs, control the trace width and spacing to match the target impedance. Use the PCB stack-up and dielectric to calculate trace geometry.<\/p>\n\n\n\n

Differential pair routing<\/h3>\n\n\n\n

Route differential pairs with equal length. Keep the spacing stable. Avoid stubs. Keep bends smooth.<\/p>\n\n\n\n

Length matching and delay<\/h3>\n\n\n\n

For buses and interfaces needing matched timing, match the routing length. Use serpentine traces for length tuning. Keep serpentine patterns smooth and short in height.<\/p>\n\n\n\n

Thermal relief and thermal pads<\/h3>\n\n\n\n

When attaching pads to large copper, use thermal relief. Make the pad connect to the plane with spokes. This helps soldering.<\/p>\n\n\n\n

Solder mask and paste mask<\/h3>\n\n\n\n

Check solder mask openings. Align paste mask for SMD parts. Make sure small pads have correct paste area.<\/p>\n\n\n\n

Design for test and assembly<\/h3>\n\n\n\n

Leave test points and assembly markers. Keep space for probes. Make placement allow soldering and inspection.<\/p>\n\n\n\n

Final routing checklist (short list)<\/h2>\n\n\n\n

\u2022 Check all nets are connected.\u2022 Run DRC and ERC checks.\u2022 Check trace width and current.\u2022 Check spacing for crosstalk and voltage.\u2022 Check decoupling and bulk capacitors.\u2022 Check plane splits and return paths.\u2022 Check thermal reliefs and pad shapes.\u2022 Check assembly and test access.<\/p>\n\n\n\n

Common errors to avoid<\/h2>\n\n\n\n

\u2022 Leaving ground plane slots under critical signals.\u2022 Running high-speed traces next to noisy power traces.\u2022 Using many 90-degree corners.\u2022 Not adding decoupling near IC pins.\u2022 Letting vias split planes badly.\u2022 Not planning fanout for dense chips.<\/p>\n\n\n\n

Closing notes<\/h2>\n\n\n\n

Routing is a key part of PCB design. A good routing job gives correct connections, good performance, and good appearance. Follow simple rules. Keep loops small. Control crosstalk and return paths. Use plane insets for edge control. Use decoupling for power noise. Use thermal reliefs for soldering. Use a reasonable grid for routing. Check the board carefully after routing.<\/p>\n\n\n\n

If you follow these basic rules, you will reduce EMI, improve signal quality, and make the board easier to build and maintain. Routing needs care. Spend time at planning and layout. Good layout pays off in time saved in test and repair, and in the final product quality.<\/p>","protected":false},"excerpt":{"rendered":"

In PCB design, routing can be seen in three broad levels. The first level is basic connectivity. This is the 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