FPC Circuit Design — Common Problems
- Overlap of pads (except SMD pads) means overlap of holes.
When holes overlap, the drill may drill the same spot many times. The drill bit can break. The hole can be damaged. This causes scrap or rework. - In multilayer boards two holes may overlap.
For example, one hole is an isolation pad. The other hole is a connection pad with thermal spokes (thermal relief). After plotting the film, the result may show only the isolation pad. The part can be scrapped.
I. Overlap of Pads
- Overlap of pads (except surface mount pads) means overlap of holes.
In drilling, the drill will drill one place many times. The drill bit can break. The hole will be damaged. - In multilayer boards two holes may overlap.
For example, one hole is an isolation pad. Another hole is a connection pad, for example a thermal-relief pad. After the film is made the image may show an isolation pad. This will cause discard.
II. Misuse of Graphic Layers
- Some graphic layers have useless traces. A four-layer board may be drawn with lines like a five-layer board. This causes confusion.
- To save time some designers use the Board layer in Protel for lines on many layers. They also draw annotation lines on the Board layer. When making photoplot data they may not select the Board layer. Then some traces are lost and the circuit is open. Or they may choose the Board layer annotation and make a short. So keep graphic layers complete and clear when you design.
- Break normal practice. For example placing component side on Bottom layer and solder side on Top layer. This makes assembly and soldering hard.
III. Random Placement of Silkscreen Text
- Text can cover pads or SMD lands. This makes electrical test and component soldering hard.
- If text is too small silk printing is hard. If text is too large letters overlap and they are hard to read.
IV. Hole Size Setting for Single-side Pads
- Single-side pads usually do not need holes. If a hole is needed mark it clearly. The hole size should be set to zero if not needed. If a numeric value is set then drill data will include that hole coordinate and cause a problem.
- If a single-side pad needs a hole mark it specially.
V. Using Filled Areas to Draw Pads
- If you draw pads with filled areas the design can pass DRC. But manufacturing cannot use such pads. These pseudo-pads cannot generate correct solder mask data. During solder mask application the filled area will be covered by solder mask. This makes component soldering hard.
VI. Power or Ground Areas that are Both Thermal Pads and Traces
- If a power or ground area is drawn as thermal-relief pads the image on the actual board will be the opposite of the design. All traces are isolation traces. Designers must be clear about this.
- When you draw several power or ground isolation groups be careful. Do not leave a gap that causes two power groups to short. Do not block the area that needs connection and split a power zone.
VII. Unclear Definition of Fabrication Stack and Layer Order
- If a single-side board is designed only on the TOP layer and no note is added it is not clear which side is front or back. The made board may be hard to solder after parts are placed.
- For example a four-layer board may be designed as TOP, MID1, MID2, BOTTOM. If the fabricator does not stack layers in the same order problems will occur. So add clear notes about layer order.
VIII. Too Many Fill Areas or Fill Areas Filled with Very Thin Lines
- Photoplot data may be incomplete and data may be lost.
- Fill areas in photoplot are drawn as many lines. This creates a very large data set. The big data volume makes data processing hard.
IX. SMD Pads Too Short
- This affects electrical continuity test. For very dense SMD parts the pad spacing is small and pad width is thin. Test pins must be staggered up and down or left and right. If the pad is too short test pins may not locate. This makes the test hard even if the part can be placed.
X. Mesh for Large Copper Areas Has Too Small Pitch
- For a large copper grid the line edge-to-edge may be too small (less than 0.3 mm). During board manufacture, after development, many small film bits can stick on the board. This can cause open lines.
XI. Large Copper Area Too Close to Board Outline
- Large copper area must keep at least 0.2 mm from the board outline. If routing or milling cuts into the copper area the copper can lift. This can cause the solder mask to peel off.
XII. Unclear Board Outline Design
- Some customers draw board outlines on Keep layer, Board layer, Top overlay layer, and these outlines do not match. This makes it hard for the PCB maker to know which outline to use.
XIII. Uneven Graphic Design
- During electroplating uneven patterns cause uneven plating. This affects quality.
XIV. When Copper Pours Are Large Use Mesh to Avoid SMT Voids
- When a copper pour area is large use a mesh pattern. This reduces the chance of bubbles or delamination during SMT reflow.
FPC Board Surface Defects and Solutions
Below I list common surface defects on FPC flexible boards and give clear causes and fixes.
1. Bubbles Between Tracks or on One Track after Development
Main cause: Bubbles between tracks or on a single track usually happen when track spacing is too narrow and the track height is too high. During screen printing the solder mask cannot reach the base material between the tall tracks. Air or moisture stays between the solder mask and base. During curing and exposure the trapped gas expands and makes bubbles. For a single track the track is too high. When the squeegee touches the track at a larger angle the solder mask cannot reach the track root. Gas stays between the track root and the solder mask. Heat makes bubbles.
Fix: Inspect during screen printing. Make sure solder mask fully covers the base and track sidewalls. Control plating current strictly in electroplating.
2. Solder Mask in Holes and Tiny Pinhole Defects in Pattern
Main cause: When screen printing is not done on time, residual ink builds up on the screen. Under squeegee pressure leftover ink can be pressed into holes. Low screen mesh count also lets ink go into holes. Dirt on the photomask causes areas that should be exposed not to expose. This gives pinholes in the pattern during exposure.
Fix: Do timely screen printing and use higher mesh count screens. Check the photomask cleanly during exposure.
3. Darkening of Copper Tracks under Solder Mask
Main cause: After wiping the board, water was not dried. The board surface got wet before solder mask printing. Or human finger or hand touched the board.
Fix: During screen printing visually check both copper surfaces for oxidation. Make sure the board is dry and clean before printing.
4. Surface Dirt and Uneven Surface
Main cause: Dirt comes from dust and flying fibers in the air. Uneven surface happens when the screen was not cleaned and leftover ink remained on the screen and was pressed to the board.
Fix: Keep a clean room and keep operators clean. Stop non-essential people from walking in the clean room. Clean the room often. During screen printing print on paper in time to remove residual ink from the screen.
5. Misregistration and Fine Cracks
Main cause: Misregistration happens when during screen printing the board is not fixed firmly. Residual ink on the screen is not removed in time and it is pressed onto the board in a pattern, so dots appear near pads. Fine cracks happen when exposure is too weak. Light dose or time is not enough, so small cracks form.
Fix: Use alignment pins to fix the board. Remove residual ink from the screen by printing on paper often. Adjust exposure so the lamp energy and exposure time give a good exposure level. Aim for an exposure index in a suitable range so cracks do not form.
6. Color Difference Between Two Sides and Missing Print (White Spots)
Main cause: The two sides have different squeegee counts during printing. Or old and new inks were mixed. For example one side uses stirred new ink and the other side uses old ink left long.
Missing print or “skip print” happens when electroplating current is too high. The plating builds the line too tall. During screen printing the high line height causes the squeegee not to deposit ink on the track sides. Another cause is the squeegee blade has a nick. The nick area does not deposit ink.
Fix: Keep the squeegee counts consistent for both sides. Do not mix old and new ink. Control plating current. Check squeegee blade for nicks.
Short Summary of Key Checks for FPC Design and Fabrication
- Check pad overlap and hole overlap before making drill data.
- Keep layer use clear and do not misuse Board layer for lines and annotation.
- Place silkscreen text away from pads. Use readable sizes.
- Mark single-side pad holes clearly or set hole size to zero.
- Do not draw pads as filled blocks if you need proper solder mask.
- Be clear about thermal reliefs and copper pours. Avoid unintended isolation.
- Document layer stack and build order for the fabricator.
- Avoid too many fill areas or very fine fill lines. Keep data size reasonable.
- Make SMD pads long enough for probe test access.
- Keep large copper mesh pitch reasonable (>= 0.3 mm between edges).
- Keep large copper areas at least 0.2 mm away from the board edge.
- Provide one clear board outline. Do not put multiple different outlines on different layers.
- Balance pattern density to avoid uneven plating.
- Use mesh in large copper pours to avoid SMT problems.
