PCB Stackup Calculator & Review Tool
Check stack thickness and preview surface microstrip impedance from an editable layer schedule.
How to Use the Stackup Tool
- Choose a starting example. Select a layer-count example, then edit the copper roles and finished copper thicknesses, plus each core or prepreg gap’s pressed thickness and material details. Treat the example as a starting point; enter the construction you intend to review.
- Inspect the changed construction. Compare the total with your target and open any mirror differences. Check each signal layer’s adjacent declared reference. For impedance work, add the Dk and test context for the selected outer dielectric gap.
- Calculate and export. For an eligible outer signal layer over its declared adjacent reference plane, calculate single-ended microstrip impedance or solve for trace width. Export the stackup and impedance scenario as a CSV for your own review or to share in a manufacturing inquiry.
Build and Review Your PCB Stackup
Layer Editor
4 copper · 3 dielectric gapsL = copper layer; D = dielectric gap. Enter finished copper and pressed dielectric thicknesses. Dk is needed only for the impedance preview.
Optional record fields: material grade / glass style, and the test frequency / method for the entered Dk. They do not look up a material or change Dk automatically.
| 레이어 | Role / type | 두께 mm | Dkfor impedance | Material notes (optional) |
|---|
Microstrip Impedance Preview
Estimate an uncoated, single-ended outer trace over an adjacent declared reference plane. The local dielectric height and Dk come directly from the layer editor.
Inner-layer, differential and coplanar lines require a different model. This preview excludes solder mask, frequency dispersion, roughness and loss.
Thickness checking works without Dk. For this estimate, use the selected gap’s Dk from your material data; the example value 4.2 is not a material specification.
Tool scope: 0.01 ≤ w/h ≤ 100, t/h ≤ 0.5, t/w ≤ 0.5 and 1 ≤ Dk ≤ 128. These are calculation guards, not manufacturing limits or an accuracy guarantee.
Calculation Methods and Assumptions
Thickness and Mirror Comparisons
The board thickness estimate is the sum of the finished copper and pressed dielectric thickness entered for each layer or gap:
T = Σ(Cu) + Σ(dielectric)
Copper and dielectric contributions are also shown separately, with the difference from an optional target thickness. Enter finished copper thickness when plating is already included; the estimate adds no extra plating. Coatings such as solder mask are outside this base total. A glass style such as 1080 or 2116 alone does not determine a pressed dielectric thickness: record the actual construction and its material properties, including Dk and its test frequency where known.
Mirror comparison checks corresponding layers for thickness and material differences. A close match can help review a symmetric construction, but matching totals or mirrored entries does not establish copper coverage balance or guarantee freedom from warpage. Layer roles also do not verify plane continuity.
Open-Source Microstrip Model
The impedance preview uses the quasi-static Hammerstad–Jensen equations with a finite copper-thickness correction, adapted in JavaScript from scikit-rf’s pinned MLine source. Width, dielectric height and copper thickness share one unit; Dk is dimensionless. The model assumes an uncoated surface trace over a continuous plane. It excludes inner-layer stripline, differential pairs, coplanar geometry, vias, solder mask, frequency dispersion, roughness and loss. The width solver searches only within the displayed geometry guards; those guards do not certify model accuracy or fabrication.
Open-source attribution and BSD 3-Clause license
JavaScript adaptation: scalar inputs, validation and bracketed width search added for FLJ PCB. Source commit f08f683460cfe495424279261471aaddac3c3b1e. Download the source license.
Copyright (c) 2010, Alexander Arsenovic All rights reserved. Copyright (c) 2020, scikit-rf Developers All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the scikit-rf nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Turn Your Stackup into a Manufacturing Review
Use the locally exported stackup as a starting point for a project review. Pair the layer schedule with the laminate family and pressed core or prepreg construction you are considering; a glass style alone does not specify the finished dielectric thickness. The PCB materials guide can help frame those material questions.
FLJ develops manufacturing stackups around the selected laminate system, pressed dielectric build and finished copper geometry. Our impedance-control service connects the target impedance and reference structure to trace-width calculations, fabrication geometry and the project’s specified coupon and TDR checks. Send inner-layer, differential or coplanar requirements too; they need the corresponding transmission-line model.
Attach the exported schedule and fabrication notes to your own inquiry, with board files, target tolerances and open material questions. We can propose a construction for your board and resolve changes before fabrication. The local export itself is not manufacturing approval.
Finished geometry.
Impedance requirements.Discuss your stackup ↗
PCB Stackup Tool FAQs
What is included in the calculated stackup thickness?
The total adds the entered finished copper and pressed dielectric thicknesses. Finished copper includes its plating contribution, so the tool adds no extra plating. Solder mask and other coatings are excluded. This is the declared stack thickness, not a guaranteed finished-board maximum.
Can a glass style such as 1080 or 2116 determine the pressed thickness?
No. Glass style alone does not specify pressed dielectric thickness. Resin content, copper foil, material system, and the manufacturer’s construction affect the result. Enter the actual pressed thickness and dielectric constant supplied for the selected construction. See PCB material properties.
Does this preview calculate inner-layer or differential impedance?
The included estimate covers static, uncoated surface microstrip with one signal trace and a reference plane. It does not model inner-layer stripline, differential pairs, solder mask, vias, coplanar geometry, frequency dispersion, or conductor roughness. Treat it as an early estimate.
Does a layer labelled Ground prove a continuous reference plane?
No. “Ground” is a layer label in the stackup record; it does not describe copper coverage, clearances, splits, or connectivity. Review the board layout to confirm the return path is continuous where the signal runs.
Are my stackup inputs submitted to a server?
The calculator and CSV export run locally in your browser; their stackup inputs are not sent to a calculator server. Normal site requests, such as loading page assets, still occur.
What should I send FLJ for a manufacturing stackup review?
Export the stackup and impedance scenario, then share the target impedance, actual laminate and pressed dielectric data, finished copper and trace geometry, and layer or return-path details. Ask the engineer to confirm material availability, finished geometry, and whether a test coupon or TDR verification is needed. Contact FLJ with the exported data.